1. 2000
  2. General-purpose Huffman encoding extension

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ITCC 2000. Los Alamitos: IEEE, p. 158-163 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  3. Hashed addressed caches for embedded pointer based codes

    Stanca, VM., Vassiliadis, S., Cotofana, SD. & Corporaal, H., 2000, In: A Bode, ...(et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 956-968 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  4. Hierarchical approach for hardware/software systems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 2000, CAS 2000 proceedings. Vol. 1. 2000 international semicondutor conference 23rd edition. D Dascalu (ed.). Piscataway: IEEE Society, p. 223-226 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Hierarchical interfaces for hardware/software systems

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2000, 14th European simulation multiconference. D Landeghem, V. (ed.). San Diego: Society for Computer Simulation International, p. 647-654 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. JAVA signal processing: FFTs with bitecodes

    Glossner, CJ., Thilo, J. & Vassiliadis, S., 2000, In : Concurrency: Practice and Experience. 10, 11-13, p. 1173-1178 6 p.

    Research output: Contribution to journalArticleScientific

  7. Link-time effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 2000, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 16, p. 503-511 9 p.

    Research output: Contribution to journalArticleScientific

  8. March tests for realistic faults in two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Records of the 2000 IEEE international workshop on memory technology, design and testing. R Rajsuman & T Wik (eds.). Los Alamitos: IEEE, p. 73-78 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. Massively parallel multiple-folded clustered processor mesh array

    Pechanek, GG., Vassiliadis, S. & Delgado-Frias, JG., 2000, Priority date 21 Mar 2000

    Research output: PatentOther research output

  10. Multi-cost routing in Max-Min fair share networks

    Gutierrez, FJ., Varvarigos, EA. & Vassiliadis, S., 2000, Proceedings. Vol. 2. S.l.: s.n., p. 1294-1304 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

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