1. 2007
  2. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. An analysis of rule-set databases in packet classification

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 110-115 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. An empirical comparison of ANSI-C to VHDL compilers: SPARK, ROCCC and DWARV

    Virginia, A., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 388-394 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Analysis of a user-space device-driver for the memcpy hardware

    Campos Soares Borrego, F. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 138-143 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Analysis of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 116-121 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Architectural Exploration of the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., Kanstein, A. & Gaydadjiev, GN., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 1-13 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. Arithmetic soft-core accelerators

    Calderon, H., 2007, Delft: H. calderon. 155 p.

    Research output: ThesisDissertation (TU Delft)

  9. Automated HDL generation: comparative evaluation

    Yankova, YD., Bertels, K., Vassiliadis, S., Meeuws, RJ. & Virginia, A., 2007, 2007 IEEE intl. Symposium on Circuits and Systems. Piscataway: IEEE Society, p. 2750-2753 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Automatic analyses of memory faulty behaviour in defective memories

    Al-Ars, Z. & Hamdioui, S., 2007, Design & Technology of Integrated Systems 2007. Hamdiuoi, S., O. A. (ed.). Piscataway: IEEE Society, p. 41-46 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Automatic hardware generation for the Molen reconfigurable architecture: a G721 case study

    Theodoropoulos, D., Yankova, YD., Kuzmanov, GK. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 380-387 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Building blocks for delay-insensitive circuits using single electron tunneling devices

    Safiruddin, S. & Cotofana, SD., 2007, 2007 7th IEEE international conference on nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 704-708 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Cache replacement policies for IP address lookups

    Guo, R., Delgado-Frias, JG. & Wong, S., 2007, 5th IASTEDintl. conf. on Circuits, Signals, and Systems. Delgado-Frias, J. G. (ed.). Zurich: ACTA Press, p. 70-75 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip

    Hansson, A., Coenen, M. & Goossens, KGW., 2007, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 149-154 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Combining voltage scaling and processor shutdown to reduce energy in embedded multiprocessors

    de Langen, P. & Juurlink, B., 2007, Proceeding of the 13th Annual conference of the ASCI. Veenman CJ Jansen FW, P. GEO. (ed.). Delft: ASCI, p. 195-202 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Communication-centric SoC debug using transactions

    Vermeulen, B., Goossens, KGW., van Steeden, R. & Bennebroek, M., 2007, 12th IEEE european Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Computing division using single-electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : IEEE Transactions on Nanotechnology. 6, 4, p. 451-459 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Configurable transactional memory

    Kachris, C. & Kulkarni, C., 2007, The fifteenth IEEE Symposium on Field Programmable Custom Computing Machine. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Congestion-controlled best--effort communication for network-on-chip

    van den Brand, J., Ciordas, C., Goossens, KGW. & Basten, T., 2007, Design, Automation & Test in Europe. s.n. (ed.). s.l.: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Customized vector instruction set architecture

    Ciobanu, CB., Spinean, B., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 128-137 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Customizing reconfigurable on-chip crossbar scheduler

    Hur, JY., Stefanov, TP., Wong, S. & Vassiliadis, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 210-215 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. DWARV: Delftworkbench automated reconfigurable VHDL generator

    Yankova, YD., Bertels, K., Kuzmanov, GK., Gaydadjiev, GN., Lu, Y. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 697-701 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Datalife time analysis in RDM+ real-time communication protocol

    Mirshokraie, S., Sabeghi, M., Bertels, K. & Naghibzadeh, M., 2007, 2007 IEEE international conference on signal processing and communications. s.n. (ed.). Piscataway: IEEE Society, p. 540-543 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Deadline vs. laxity as a decision parameter in fuzzy real-time scheduling

    Sabeghi, M., Bertels, K. & Naghibzadeh, M., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 354-358 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Design & Technology of Integrated Systems in Nanoscala era

    Hamdioui, S. & Orailoglu, A., 2007, Piscataway: IEEE Society. 260 p.

    Research output: Book/ReportBookProfessional

  26. Design & algorithms for packet and content inspection

    Sourdis, I., 2007, Delft: s.l.. 162 p.

    Research output: ThesisDissertation (TU Delft)

  27. Design and implementation of reliable wireless sensor networks-a case study in commuter trains

    Kootkar, S. & Al-Ars, Z., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 303-306 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Design considerations for a domain specific vector microarchitecture

    Spinean, B., Ciobanu, CB., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 178-184 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

    Yseboodt, L., De Nil, M., Huisken, J., Berekovic, M., Zhao, Q., Bouwens, F. & van Meerbergen, J., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 385-395 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Design space exploration of configuration manager for network processing applications

    Kachris, C. & Vassiliadis, S., 2007, International conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Glossner, J. Blume, H., G. G. (ed.). Piscataway: IEEE Society, p. 34-40 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Dynamic FPGA reconfigurations with run-time region delimitation

    Bok van der, K., Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & van Genderen, AJ., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 201-207 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Embedded Computer Systems: Architectures, Modeling, and Simulation

    Vassiliadis, S., Berekovic, M. & Hämäläinen, TD., 2007, Heidelberg: Springer. 463 p.

    Research output: Book/ReportBookProfessional

  33. FLUX interconnection networks on demand

    Vassiliadis, S. & Sourdis, I., 2007, In : Journal of Systems Architecture. 53, 10, p. 777-793 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. FPGA area allocation for parallel C applications

    Sima, VM., Panainte, E. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 369-374 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Fault tolerant structures for nanoscale gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2007, 2007 7th IEEE international conference on nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 605-610 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Fine-and coarse-grain reconfigurable computing

    Vassiliadis, S. & Soudris, D., 2007, Heidleberg: Springer. 378 p.

    Research output: Book/ReportBookProfessional

  37. Floating-point matrix multiplication in a polymorphic processor

    Kuzmanov, GK. & Oijen van, WM., 2007, ICFPT 2007. Takeshi Ikenaga Hideharu Amano, A. Y. (ed.). s.l., p. 249-252 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. H.264/AVC HDTV motion compensation soft IP

    Pereira de Azevedo Filho, AP., Agostini, L., Susin, A. & Bampi, S., 2007, IP07 proceedings. s.m. (ed.). Wordpress.com, p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. HaRTES toolchain early evaluation: profiling, compilation and HDL generation

    Bertels, K., Kuzmanov, GK., Panainte, E., Gaydadjiev, GN., Yankova, YD., Sima, VM., Sigdel, K., Meeuws, RJ. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 402-408 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Hardware acceleration of sequence alignment algorithms: an overview

    Hasan, L., Al-Ars, Z. & Vassiliadis, S., 2007, Design & Technology of Integrated Systems 2007. Hamdiuoi, S., O. A. (ed.). Piscataway: IEEE Society, p. 96-101 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Hashing functions performance in packet classification

    Ahmadi, M. & Wong, S., 2007, Proceeding of the 2nd International conference on the latest advances in networks. s.n. (ed.). s.l., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. High speed reconfigurable computation for electronic instrumetation in space applications

    Lampridis, D., Cotofana, SD. & Kraft, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 221-227 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. High-bandwidth address generation unit

    Calderon, H., Galuzzi, C., Gaydadjiev, GN. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 251-262 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Instruction-level fault tolerance configurability

    Borodin, D., Juurlink, B. & Vassiliadis, S., 2007, International conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Glossner, J. Blume, H., G. G. (ed.). Piscataway: IEEE Society, p. 110-117 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

    Blume, H., Gaydadjiev, GN., Glossner, CJ. & Knijnenburg, PMW., 2007, Piscataway: IEEE Society. 214 p.

    Research output: Book/ReportBookProfessional

  46. Loop parallelization for reconfigurable architectures

    Dragomir, OS., Panainte, E. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 298-302 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. MORPHEUS: heterogeneous reconfigurable computing

    Thoma, F., Kühnle, M., Bonnot, P., Panainte, E., Bertels, K., Goller, S., Schneider, A., Guyetant, S., Schüler, E., Müller-Glaser, KD. & Becker, J., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 409-414 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. MT-adres: multithreading on coarse-grained reconfigurable architecture

    Wu, K., Kanstein, A., Madsen, J. & Berekovic, M., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 26-38 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  49. Manifestation of precharge faults in high speed DRAM devices

    Al-Ars, Z., Hamdioui, S. & Gaydadjiev, GN., 2007, 2007 IEEE workshop on Design and diagnostics of electronic circuits and systems. Gramatova, E. Girard, P., K. E. & Garbolina, T. (eds.). Piscataway: IEEE Society, p. 179-184 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Manufacturability issues of redundant nanogates

    Martorell, F., Cotofana, SD. & Rubio, A., 2007, 2007 International semiconductor conference. s.n. (ed.). Piscataway: IEEE Society, p. 49-52 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.2624/AVC deblocking filter

    Arbelo, C., Kanstein, A., López, S., López, JF., Berekovic, M., Sarmiento, R. & Mignolet, J-Y., 2007, IEEE 2007 Intl. conference on Design, Automation and Test in Europe. s.n. (ed.). Piscataway: IEEE Society, p. 177-182 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Matchmaking through economic-based approaches in ad-hoc grids

    Pourebrahimi, B. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 349-353 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. Matrix multiplication implementation in the MOLEN polymorphic processor

    Oijen van, WM. & Kuzmanov, GK., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 242-249 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. On effective computation with single electron tunneling devices

    Cotofana, SD., 2007, DCIS2007. s.n. (ed.). s.l., p. 293-298 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. OpenFPGA corelib core library interoperability effort

    Wirthlin, M. & Kuzmanov, GK., 2007, Third annual Reconfigurable Systems Summer Institute. s.n. (ed.). s.l.: Board of trustees of the University of Illinois, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Optimizing cache performance of the discrete wavelet transform using a visualization tool

    Tao, J., Shahbahrami, A., Juurlink, B., Buchty, R., Karl, W. & Vassiliadis, S., 2007, 9th IEEE Intl. Symposium on Multimedia. s.n. (ed.). USA: IEEE CPS, p. 153-160 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Optimizing test length for soft faults in DRAM devices

    Al-Ars, Z., Hamdioui, S. & Gaydadjiev, GN., 2007, 25th IEEE VLSI Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 59-66 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. PPM recuction on embedded memories in system on chip

    Hamdioui, S., Al-Ars, Z., Jimenez, J. & Calero, J., 2007, 12th IEEE European Test Symposium. Lisa O'Conner (ed.). Piscataway: IEEE Society, p. 85-90 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. Parallelism utilization in embedded reconfigurable computing systems: a survey of recent trends

    Ostadzadeh, SA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 338-348 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs

    Hur, JY., Wong, S. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 49-60 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  61. Performance evaluation of real-time message delivery in RDM algorithm

    Mirshokraie, S., Sabeghi, M., Naghibzadeh, M. & Bertels, K., 2007, Third Intl. conference on Networking and services. s.n. (ed.). Piscataway: IEEE Society, p. 74-79 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. Performance improvement of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 211-214 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Polymorphic instruction set computers

    Kuzmanov, GK. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 217-254 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  64. Power and performance profiling of lossless compression algorithms in ultra-low-power embedded cores

    Strydis, C. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 375-379 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Predator: a predictable SDRAM memory controller

    Akesson, B., Goossens, KGW. & Ringhofer, M., 2007, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 251-256 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Quantitative prediction for early design space exploration in Delft workbench: an outlook

    Meeuws, RJ., Sigdel, K., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 311-316 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. RDM+: a new mac layer real-time communication protocol

    Sabeghi, M., Naghibzadeh, M. & Bertels, K., 2007, IEEE Samoff symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Real-time FPGA-implementation for blue-sky detection

    Quach, NT., Zafarifar, B. & Gaydadjiev, GN., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 76-82 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Reconfigurable network processing platforms

    Kachris, C., 2007, Delft: s.l.. 143 p.

    Research output: ThesisDissertation (TU Delft)

  70. Reconfigurable universal adder

    Calderon, H., Gaydadjiev, GN. & Vassiliadis, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 186-191 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Reliability Analysis of Hierarchical Systems using Statistical Moments

    Reijns, GL. & van Gemund, AJC., 2007, In : IEEE Transactions on Reliability. 56, p. 1-8 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  72. Reverse engineering java card applets using power analysis

    Vermoen, D., Witteman, M. & Gaydadjiev, GN., 2007, Proceedings Intl. Workshop on Information Security Theory and Practices. Bilas, A. Sauveron, D., M. K. (ed.). Heidelberg: Springer, p. 138-149 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Run-time partial reconfiguration for removal, placement and routing on the virtex-II-pro

    Raaijmakers, S. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 679-683 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. SARC power estimation methodology

    Ludovici, D. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 151-155 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. SIMD vectorization of histogram functions

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 174-179 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Scheduling in high performance buffered crossbar switches

    Mhamdi, LL., 2007, Delft: L. Mhamdi. 166 p.

    Research output: ThesisDissertation (TU Delft)

  77. Secure computing on reconfigurable systems

    Chaves Fernandes, R., 2007, Delft: s.l.. 167 p.

    Research output: ThesisDissertation (TU Delft)

  78. Slack exploitation for aggressive dynamic power reduction in SoC

    Milutinovic, A., Goossens, KGW. & Smit, GJM., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 317-322 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Static cache partitioning robustness analysis for embedded on-chip multi-processors

    Molnos, AM., Cotofana, SD., Heijligers, MJM. & van Eijndhoven, JTJ., 2007, Transactions on high-performance embedded architectures and compilers I. Bodin, F Stenström, P, OB. M. & McKee, S (eds.). Berlin: Springer, p. 279-297 360 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  80. Suitability of tile-based rendering for low-power 3D graphics accelerators

    Antochi, I., 2007, Delft: I. Antochi. 148 p.

    Research output: ThesisDissertation (TU Delft)

  81. Supporting the linux operating system on the MOLEN processor prototype

    Campos Soares Borrego, F., Breijer, B. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 205-210 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. Synthesis of regular expressions targeting FPGAs: current status and open issues

    Bispo, JCVM., Sourdis, I., Cardoso, JMP. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 179-190 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  83. Systematic customization of on-chip crossbar intervconnects

    Hur, JY., Stefanov, TP., Wong, S. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 61-72 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  84. Testing of modern semiconductors memory structures

    Gaydadjiev, GN., 2007, Delft: G. Gaydadjiev. 120 p.

    Research output: ThesisDissertation (TU Delft)

  85. The Challenges of Intra-Spacecraft Wireless Data Interfacing

    Amini, R., Gill, EKA. & Gaydadjiev, GN., 2007, 58th International Astronautical Congress 2007. s.n. (ed.). Hyderabad, India: IAF/IAA, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. The Future of computing

    Bertels, K., Cotofana, SD., Gaydadjiev, GN., Goossens, KGW., Hamdioui, S., Juurlink, B., van Genderen, AJ. & Wong, S., 2007, Delft: Computer Engineering TUDelft. 143 p.

    Research output: Book/ReportBookProfessional

  87. The Molen compiler for reconfigurable architectures

    Panainte, E., 2007, Delft: E. Moscu-Panainte. 137 p.

    Research output: ThesisDissertation (TU Delft)

  88. The Molen compiler for reconfigurable architectures

    Panainte, E., 2007, Delft: E. Moscu-Panainte. 137 p.

    Research output: ThesisDissertation (TU Delft)

  89. The spiral search: a linear complexity algorithm for the generation of convex MIMO instruction-set extensions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, ICFPT 2007. Takeshi Ikenaga Hideharu Amano, A. Y. (ed.). s.l., p. 337-340 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. Trade-offs between voltage scaling and processor shutdown for low-energy embedded multiprocessors

    de Langen, PJ. & Juurlink, B., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 75-85 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. Trade-offs in the configuration of a network on chip for multiple use-cases

    Hansson, A. & Goossens, KGW., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Transaction-based communication-centric debug

    Goossens, KGW., Vermeulen, B., van Steeden, R. & Bennebroek, M., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. Trends in low power handset software defined radio

    Glossner, CJ., Iancu, D., Moudgill, M., Schulte, M. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 313-321 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. Two-dimensional memory implementation with multiple data patterns

    Vitkovskiy, A., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 185-190 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Undisrupted quality-of-service during reconfiguration on multiple applications in networks on chip

    Hansson, A., Coenen, M. & Goossens, KGW., 2007, Design, Automation & Test in Europe. s.n. (ed.). s.l.: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. Vectorized aes core for high-throughput secure environments

    Pericas, M., Chaves, PC., Gaydadjiev, GN. & Vassiliadis, S., 2007, The future of computing. Gaydadjiev, G Bertels, K, C. S. & Genderen van, A Hamdioui, S, J. B. (eds.). Delft: Computer Engineering TUDelft, p. 91-100 143 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  97. Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

    Amory, A., Goossens, KGW., Marinissen, E., Lubaszewski, M. & Moraes, F., 2007, In : IET Computers and Digital Techniques. 1, 3, p. 197-206 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  98. 2008
  99. A cache-based hardware accelerator for memory data movements

    Campos Soares Borrego, F., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)

  100. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  101. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  102. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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