1. 2008
  2. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. A hybrid cross layer architecture for wireless protocol stacks

    Chang, Z. & Gaydadjiev, GN., 2008, 2008 international wireless communications and mobile computing conference. s.n. (ed.). Piscataway: IEEE Society, p. 279-285 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A memory-optimized bloom filter using an additional hashing function

    Ahmadi, M. & Wong, S., 2008, IEEE GLOBECOM 2008. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A novel approach for accelerating the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z. & Nawaz, Z., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 40-45 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A partially buffered crossbar packet switching architecture and its scheduling

    Mhamdi, LL., 2008, IEEE Intl. Symposium on Computers and Communications. s.n. (ed.). s.l.: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A systolic architecture for the Smith-Waterman algorithm with high performance cell design

    Hasan, L., Khawaya, YM. & Bais, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 35-42 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Acceleration of Smith-Waterman using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

    Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Adaption to dynamic resource availability in ad hoc grids through a learning mechanism

    Pourebrahimi, B. & Bertels, KLM., 2008, 2008 IEEE 11th Intl. Conf. on Computational Science and Engineering. s.n. (ed.). s.l.: s.n., p. 171-178 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Adaptive gaussian mixture for skin color segmentation

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2008, Proceeding of World Academy of Science, Engineering and Technology. s.n. (ed.). s.l.: WASET org., p. 1-6 6 p. (World Academy of Science, Engineering and Technology. Proceedings; vol. 31).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. An approach for optimal bandwidth allocation in packet processing systems

    Ahmadi, M. & Wong, S., 2008, CNSR 2008 conference. s.n. (ed.). s.l.: s.n., p. 208-214 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. An efficient RNS to binary converter using the moduli set {2n+1, 2n, 2n-1}

    Gbolagade, KA. & Cotofana, SD., 2008, Conference on Design of Circuits and Integrated Systems. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. An efficient algorithm for free resources management on the FPGA

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1095-1098 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Analyses of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, 2008 IEEE International Symposium on Circuits and Systems. s.n. (ed.). s.l., p. 488-491 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 189-194 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Applying dataflow analysis to dimension buffers for guaranteed performance in networks on chip

    Hansson, A., Wiggers, M., Moonen, A., Goossens, KGW. & Bekooij, M., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 211-212 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Architecture enhancements for the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., de Sutter, B. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 66-81 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  23. Auction protocols for resource allocations in ad-hoc grids

    Pourebrahimi, B. & Bertels, KLM., 2008, In : Lecture Notes in Computer Science. LNCS5168, p. 520-533 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. Automatic instruction-set extensionswith the linear complexity spiral search

    Galuzzi, C., Theodoropoulos, D., Meeuws, RJ. & Bertels, K., 2008, 2008 international conference on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 31-36 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Automating defects simulation and fault modeling for SRAMs

    Di Carlo, S., Prinetto, P., Scionti, A. & Al-Ars, Z., 2008, IEEE Intl. High Level Design Validation and Test workshop 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Avoiding conversion and rearrangement overhead in SIMD architectures

    Shahbahrami, A., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)

  27. BIST enhancement for detecting bit/byte write enable faults in SOC SCRAMs

    Hamdioui, S., Al-Ars, Z., Jimenez, J. & Calero, J., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. BRAM-LUT tradeoff on a polymorphic DES design

    Chaves Fernandes, R., Donchev, B., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 55-65 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  29. Bandwidth analyses for reusing functional interconnect as test access mechanism

    van den Berg, A., Ren, R., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2008, 13th European test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 21-26 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Bioinformatics specific cell BE ISA extensions

    Isaza, S. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 52-55 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Bitstream compression techniques for virtex 4 FPGAS

    Stefan, RA. & Cotofana, SD., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 323-328 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Building blocks for fluctuation based calculation in single electron tunneling technology

    Safiruddin, S., Cotofana, SD., Peper, F. & Lee, J., 2008, 2008 eighth IEEE conference on nanotechnology. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. CMOS scaling impacts on reliability, what do we understand?

    Seyab, MSK., Haron, NZB. & Hamdioui, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 260-266 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. Casta diva-a design for variability platform

    Cotofana, SD. & Meenderinck, CH., 2008, 2008 Intl. Semiconductor Conference. s.n. (ed.). s.l.: IEEE Society, p. 373-376 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Comparison between color and texture features for image retrieval

    Shahbahrami, A., Borodin, D. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 361-371 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Compiler and openMP framework to allow dynamics hardware allocation on reconfigurable platforms

    Sima, VM. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 108-111 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Compositional, dynamic cache management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD. & Heijligers, MJM., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 991-996 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Cost-efficient SHA hardware accelerators

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 999-1008 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  39. Cross-layer designs architecture for LEO satellite ad hoc network

    Chang, Z. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. 5031, p. 164-176 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. Current trends in resource management of recongigurable systems

    Sabeghi, M. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 89-93 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Data locality optimization based on comprehensive knowledge of the cache miss reason: a case study with DWT

    Tao, J. & Shahbahrami, A., 2008, 10th IEEE intl. Conf. on High Performance Computing and Communications. s.n. (ed.). s.l.: IEEE Society, p. 304-311 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Debugging distributed-shared-memory communication at multiple granularities in network on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 3-12 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Debugging distributed-shared-memory communication at multiple granularities in networks on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE international symposium on networks-on-chip. s.n. (ed.). Piscataway: IEEE Society, p. 3-12 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Defect oriented testing of the strap problem under process variations in DRAMs

    Al-Ars, Z., Hamdioui, S., van de Goor, AJ. & Mueller, G., 2008, Proc. International Test Conference 2008. s.n. (ed.). Washington DC: ITC, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Design and test of integrated circuits in Nano era: what is next?

    Hamdioui, S., 2008.

    Research output: Contribution to conferenceAbstractScientific

  46. Design trade-offs in customized on-chip crossbar schedulers

    Hur, JY., Wong, S. & Stefanov, TP., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  47. Efficient multicast support in high-speed packet switches

    Mhamdi, LL., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of Networks. 2, 3, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  48. Efficient tests and DFT for RAM address decoder delay faults

    Hamdioui, S. & Al-Ars, Z., 2008, 3rd International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. 225-230 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Emerging crossbar-based hybrid nanoarchitectures for future computing systems

    Haron, NZB. & Hamdioui, S., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Evaluation of SRAM faulty behavior under bit line coupling

    Al-Ars, Z. & Hamdioui, S., 2008, 3rd International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. 231-236 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Exploiting parallelism of deblocking filter of H.264 on DTA architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 55-58 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Extending loop unrolling and shifting for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, Architecture and Compilers Embedded Systems symposium. s.n. (ed.). s.l.: s.n., p. 61-64 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. FPGA Implementation of Parallel Histogram Computation

    Shahbahrami, A., Hur, JY., Juurlink, B. & Wong, S., 2008, 2nd HIPEAC workshop on Reconfigurable Computing. s.n. (ed.). HiPEAC, p. 63-72 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. FPGA implementation of low-frequency GPR signal algorithm using frequency stepped chirp signals in the time domain.

    Kyovtorov, VA., Kabakchiev, C., Behar, V., Kuzmanov, GK., Garvanov, I. & Doukovska, L., 2008, IEEE Intl. Radar Symposium 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. GRAAL: a framework for low-power 3D graphics accelerators

    Juurlink, B., Crisu, D., Antochi, I., Cotofana, SD. & Vassiliadis, S., 2008, In : IEEE Computer Graphics and Applications. 28, 4, p. 63-73 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  56. Generalized matrix method for efficient residue to decimal conversion

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Asia pacific conference on circuits ans systems. s.n. (ed.). Piscataway: IEEE Society, p. 1414-1417 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Generic loop parallelization for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 35-39 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z., Nawaz, Z. & Bertels, K., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 135-140 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. Hardwired NOC infrastructure with integrated configuration and functional architectures

    Wahlah, MA. & Goossens, KGW., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 122-125 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. Hardwired networks on chip in FPGAs to unify functional and configuration interconnects

    Goossens, KGW., Bennebroek, M., Hur, JY. & Wahlah, MA., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: IEEE Society, p. 45-54 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. High level quantitative interconnect estimation for early design space exploration

    Meeuws, RJ., Sigdel, K., Yankova, YD. & Bertels, K., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 317-320 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. High quality simulation tool for memory redundancy algorithms

    Yamasaki, K., Hamdioui, S., Al-Ars, Z., van Genderen, AJ. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 133-138 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. High-bandwidth address generation unit

    Galuzzi, C., Gou, C., Calderon, H., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  64. ImpBench -a novel benchmark suite for biomedical, microelectronic implants

    Strydis, C., Kachris, C. & Gaydadjiev, GN., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 82-91 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Implementing the 2-d wavelet transform on SIMD-enhanced general-purpose processors

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2008, In : IEEE Transactions on Multimedia. 10, 1, p. 43-51 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  66. Instruction-level fault tolerance configurability

    Borodin, D., Juurlink, B., Hamdioui, S. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  67. Intelligent merging online task placement algorithm for partially reconfigurable systems

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1346-1351 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Leakage-aware multiprocessor scheduling

    de Langen, PJ. & Juurlink, B., 2008, In : Journal of V LSISignal Processing. p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  69. Loop optimizations for reconfigurable architectures

    Dragomir, OS., Stefanov, TP. & Bertels, KLM., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 215-218 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. Loop unrolling and shifting for reconfigurable architectures

    Dragomir, OS., Stefanov, TP. & Bertels, KLM., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 167-171 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Low power microarchitecture with instruction reuse

    Pratas, F., Gaydadjiev, GN., Berekovic, M., Sousa, L. & Kaxiras, S., 2008, Computing Frontiers 2008. s.n. (ed.). s.l.: s.n., p. 149-158 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. MRC technique for RNS to decimal conversion using the moduli set{2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 318-321 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Market formulation for resource allocation in an ad-hoc grid

    Pourebrahimi, B., Alima, LO. & Bertels, K., 2008, Second IEEE international conference on self-adaptive and self-organizing systems workshop. s.n. (ed.). Piscataway: IEEE Society, p. 254-259 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. Memory copies in multi-level memory systems

    de Langen, PJ. & Juurlink, B., 2008, ASAP 2008 Conference proceedings. s.n. (ed.). IEEE Society, p. 287-292 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. Memory organization with multi-pattern parallel accesses

    Vitkovski, A., Kuzmanov, GK. & Gaydadjiev, GN., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1420-1425 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Merged computation for whirlpool hashing

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 272-275 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. On incorporating reconfigurable architectures into grid environments using gridsim

    Ahmadi, M. & Wong, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 5-10 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. On-the-fly attestation of reconfigurable hardware

    Chaves Fernandes, R., Kuzmanov, GK. & Sousa, L., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 71-76 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Online hardware task scheduling and placement algorithm on partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 306-311 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  80. OpenFPGA corelib core library interoperability effort

    Withlin, M., Poznanovic, D. & Kuzmanov, GK., 2008, In : Parallel Computing. 34, 4-5, p. 231-244 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. Optimal unroll factor for reconfigurable architectures

    Dragomir, OS., Panainte, E., Bertels, K. & Wong, S., 2008, In : Lecture Notes in Computer Science. LNCS 4943, p. 4-14 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  82. Optimization of content-based image retrieval functions

    Shahbahrami, A. & Juurlink, B., 2008, Tenth IEEE International Symposium on Multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 607-612 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Parallel Scalability of H.264

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Alvarez, M., Juurlink, B. & Ramirez, A., 2008, First Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG-1). s.n. (ed.). s.l., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Parallel scalability of video decoders

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, In : Journal of V LSISignal Processing. p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  85. Partilially reconfigurable point-to-point FPGA interconnects

    Hur, JY., Wong, S. & Vassiliadis, S., 2008, In : International Journal of Electronics. 95, 7

    Research output: Contribution to journalArticleScientificpeer-review

  86. Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs

    Hur, JY., Goossens, KGW. & Mhamdi, LL., 2008, 16th IFIP/IEEE Intl. Conference on Very Large Scale Integration. s.l. (ed.). s.n., p. 224-232 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. Preliminary analyses of the cell BE processor limitations for sequence alignment applications

    Isaza, S., Sanchez, F., Gaydadjiev, GN., Ramirez, A. & Valero, M., 2008, In : Lecture Notes in Computer Science. LNCS5114, p. 53-64 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  88. Profiling of lossless-compression algorithms for a novel biomedical-implant

    Strydis, C. & Gaydadjiev, GN., 2008, ESWEEK 2008 Compilation Proceedings. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 109-114 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Profiling of symmetric -encryption algorithms for a novel biomedical-implant architecture

    Strydis, C., Zhu, D. & Gaydadjiev, GN., 2008, 2008 Computing Frontiers. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 231-240 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. Rapid prototyping of the data-driven chip-multiprocessor (D2-CMP) using FPGAs

    Tatas, K., Kyriacou, C., Evripidou, P., Trancoso, P. & Wong, S., 2008, In : Parallel Processing Letters. 18, 2, p. 291-306 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Real-time scheduling using credit-controlled static-priority arbitration

    Akesson, B., Steffens, L., Strooisma, E. & Goossens, KGW., 2008, 14th IEEE intl. Conf. on Embedded and Real-Time Computing Systems and Applications. s.n. (ed.). Piscataway: IEEE Society, p. 3-14 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Reconfigurable architectures in collborative grid computing: an approach

    Wong, S. & Ahmadi, M., 2008, Second Intl. Conf. on Networks for Grid Applicatiojns. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. Regular expression matching in reconfigurable hardware

    Sourdis, I., Vassiliadis, S., Bispo, JCVM. & Cardoso, JMP., 2008, In : Journal of Signal Processing Systems: the journal of DSPtechnologies. 51, 1, p. 99-121 23 p.

    Research output: Contribution to journalArticleScientificpeer-review

  94. Residue number system operands to decimal conversion for 3-moduli sets

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Intl. 51st Midwest Symp. on Circuits and Systems. s.n. (ed.). s.l.: IEEE Society, p. 791-794 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Resiurce allocation and openMP extensions for a reconfigurable platform

    Sima, VM., Panainte, E. & Bertels, KLM., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 1-3 3 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. Resource allocation algorithm and openmp extensions for parallel execution on a heterogeneous reconfigurable platform

    Sima, VM., Panainte, E. & Bertels, KLM., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 651-654 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Resource allocation in market-based grids using a history-based pricing mechanism

    Pourebrahimi, B., Ostadzadeh, SA. & Bertels, KLM., 2008, Advances in computer and information sciences and engineering. Sobh, T. (ed.). s.l.: Springer, p. 97-100 590 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  98. Resource allocation in market-based grids using a history-based pricing mechanism

    Pourebrahimi, B., Ostadzadeh, SA. & Bertels, KLM., 2008, Intl. Joint Conference on Computer, Information, and Systems Sciences, and Engineering. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. Rule-set database inspection: towards knowledge utilization in packet processing

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2008, Proceedings of the third international conference on the latest advances in networks. s.n. (ed.). s.l.: s.n., p. 153-158 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. Run-time adaptable architectures for heterogeneous behavior embedded systems

    Schneider Beck, AC., Rutzig, MB., Gaydadjiev, GN. & Carro, L., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 111-124 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  101. SAMS: Single-affiliation memory-stride parallel memory scheme

    Gou, C., Kuzmanov, GK. & Gaydadjiev, GN., 2008, Computing Frontiers 2008. s.n. (ed.). s.l.: s.n., p. 359-367 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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