1. (When) will CMPs hit the power wall?

    Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  2. 2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE Computer Society, p. 436-440 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  3. 2007 International conference on field programmable logic and applications

    Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

    Research output: Book/ReportBookProfessional

  4. 3-Tier reconfiguration model for FPGAs using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 504-509 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. 3D graphics benchmarks for low-power architectures

    Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 18-22 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. 3D graphics tile-based systolic scan-conversion

    Crisu, D., Vassiliadis, S., Cotofana, SD. & Liuha, P., 2004, Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on. Matthews, MB. (ed.). Piscataway: IEEE Society, p. 517-521 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. 3D stacked wide-operand adders: A case study

    Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE Computer Society, p. 133-141 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. 3D-COSTAR: a cost model for 3D stacked ICs

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE Computer Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. 3D-TV rendering on a multiprocessor system on a chip

    Li, X., van Eijndhoven, JTJ. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 271-282 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

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