1. (When) will CMPs hit the power wall?

    Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. 2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE, p. 436-440 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  3. 2007 International conference on field programmable logic and applications

    Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

    Research output: Book/ReportBookProfessional

  4. 3-Tier reconfiguration model for FPGAs using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 504-509 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. 3D graphics benchmarks for low-power architectures

    Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 18-22 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. 3D graphics tile-based systolic scan-conversion

    Crisu, D., Vassiliadis, S., Cotofana, SD. & Liuha, P., 2004, Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on. Matthews, MB. (ed.). Piscataway: IEEE Society, p. 517-521 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. 3D stacked wide-operand adders: A case study

    Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE, p. 133-141 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. 3D-COSTAR: a cost model for 3D stacked ICs

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. 3D-TV rendering on a multiprocessor system on a chip

    Li, X., van Eijndhoven, JTJ. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 271-282 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  11. 3D/ 2.5D stacked IC cost modeling and test flow selection

    Hamdioui, S., 2014, p. 1-1. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  12. 64-bit floating-point FPGA matrix multiplication

    Dou, Y., Vassiliadis, S., Kuzmanov, GK. & Gaydadjiev, GN., 2005, Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays (FPGA '05). s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 86-95 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. 7/3 and 7/2 Counters implemented in single electron technology

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 344-350 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  14. A 2D adressing mode for multimedia applications

    Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  15. A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

    Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A 3D-audio reconfigurable processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. A CMOS flip-flop featuring embedded threshold logic functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 388-392 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. A CMOS semi-custom chip for mixed signal designs

    van Genderen, AJ., Cotofana, SD., de Graaf, G., Kaichouhi, A., Liedorp, J., Nouta, R., Pertijs, MAP. & Verhoeven, CJM., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 191-196 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  20. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology

    Erozan, A. T., Wang, G. Y., Bishnoi, R., Aghassi-Hagmann, J. & Tahoori, M. B., 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 6, p. 1485-1495 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms

    Ahmed, N., Bertels, K. & Al-Ars, Z., Dec 2016, 2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Tian, T., Jiang, Q., Liu, Y., Burrage, K., Song, J., Wang, Y., Hu, X., Morishita, S., Zhu, Q. & Wang, G. (eds.). Piscataway, NJ: IEEE, p. 1421-1428 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. A Computation-In-Memory Accelerator Based on Resistive Devices

    Du Nguyen, H. A., Yu, J., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 2019, Proceedings of the International Symposium on Memory Systems. New York: Association for Computing Machinery (ACM), p. 19-32 14 p. (ICPS: ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

    Medeiros, G. C., Cem Gursoy, C., Wu, L., Fieback, M., Jenihhin, M., Taouil, M. & Hamdioui, S., 2020, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). Institute of Electrical and Electronics Engineers (IEEE), p. 792-797 6 p. 9116278. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A DfT architecture and tool flow for 3-D SICs with test data compression, embedded cores, and multiple towers

    Papameletis, C., Keller, B., Chickermane, V., Hamdioui, S. & Marinissen, EJ., 2015, In : IEEE Design & Test. 32, 4, p. 40-48 9 p.

    Research output: Contribution to journalArticleProfessional

  26. A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons

    Yu, J., Hogervorst, T. & Nane, R., 2017, GLSVLSI '17 Proceedings of the on Great Lakes Symposium on VLSI 2017 . New York: Association for Computing Machinery (ACM), p. 71-76 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model

    Fang, J., Chen, J., Lee, J., Al-Ars, Z. & Hofstee, P., 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): Proceedings. IEEE, p. 335-335 1 p. 8735518

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. A Heterogeneous Quantum Computer Architecture

    Fu, X., Riesebos, L., Lao, L., García Almudever, C., Sebastiano, F., Versluis, R., Charbon, E. & Bertels, K., 2016, Proceedings of the ACM International Conference on Computing Frontiers, CF '16. New York: Association for Computing Machinery (ACM), p. 323-330 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. A Java-enabled DSP

    Glossner, CJ., Schulte, MJ. & Vassiliadis, S., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 307-327 19 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  31. A Locality-Aware Hash-Join Algorithm

    Fang, J., Hidders, J., Bertels, K., Lee, J. & Hofstee, P., 2016, p. 1-4. 4 p.

    Research output: Contribution to conferenceAbstractScientific

  32. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. A Microarchitecture for a Superconducting Quantum Processor

    Fu, X., Rol, M. A., Bultink, C. C., van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., Almudéver, C. G., DiCarlo, L. & Bertels, K., 2018, In : IEEE Micro. 38, 3, p. 40-47 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  35. A Non-Intrusive Online FPGA Test Scheme Using A Hardwired Network on Chip

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 351-359 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. A Novel Dynamic Task Scheduling Algorithm for Grid Networks with Reconfigurable Processors

    Nadeem, MF., Ostadzadeh, SA., Ahmadi, M., Nadeem, M. & Wong, JSSM., 2011, 5th HiPEAC Workshop on Reconfigurable Computing. s.n. (ed.). s.l.: HiPEAC, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit

    Weller, D. D., Erozan, A. T., Rasheed, F., Bishnoi, R., Aghassi-Hagmann, J. & Tahoori, M. B., 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 6, p. 1496-1504 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  38. A Novel Virtual Age Reliability Model for Time-toFailure Prediction

    Wang, Y. & Cotofana, SD., 2010, IEEE International Integrated Reliability Workshop Final Report. Young, C. & Geilenkeuser, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 102-105 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. A Reconfigurable Audio Beamforming Multi-Core Processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Symposium on Applied Reconfigurable Computing. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R. & El-Ghazawi, T. (eds.). Heidelberg: Springer, p. 3-14 12 p. (Lecture Notes in Computer Science; vol. 6578).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. A Security Verification Template to Assess Cache Architecture Vulnerabilities

    Ghasempouri, T., Raik, J., Paul, K., Reinbrecht, C., Hamdioui, S. & Taouil, M., 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): Proceedings. IEEE, p. 1-6 6 p. 9095707

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. A Simulation Framework for Reconfigurable Processors in Large-scale Distributed Systems

    Nadeem, MF., Ostadzadeh, SA., Nadeem, M., Wong, JSSM. & Bertels, KLM., 2011, International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Sheu, JP. & Wang, CL. (eds.). Piscataway: IEEE Society, p. 352-360 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. A Sparse VLIW Instruction Encoding Scheme Compatible with Generic Binaries

    Brandon, A., Hoozemans, J., van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck Filho, A. C. & Wong, S., Jan 2016. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  43. A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

    Yang, B., Popovici, E., Quille, M. A., Amann, A. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 79-84 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  45. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  46. A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2011, Proceedings 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 818-822 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. A Uni¿ed Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits

    Wang, Y., Cotofana, SD. & Fang, L., 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures. Moritz, CA. & O'Connor, I. (eds.). Piscataway, NJ, USA: IEEE Society, p. 175-180 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. A VLIW softcore processor with dynamically adjustable issue-slots

    Anjam, F., Nadeem, M. & Wong, JSSM., 2010, 2010 intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. A cache architecture for counting bloom filters

    Ahmadi, M. & Wong, S., 2007, 15th International conference on networks. s.n. (ed.). Piscataway: IEEE Society, p. 218-223 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. A cache-based hardware accelerator for memory data movements

    Campos Soares Borrego, F., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)

  51. A case for hardware task management support for the StarSS programming

    Meenderinck, CH. & Juurlink, BHH., 2010, 13th Euromicro conf. on digital systems design, architectures, methods and tools. s.n. (ed.). Piscataway: IEEE Society, p. 347-354 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. A comparison between processor architectures for multimedia applications

    Shahbahrami, A., Juurlink, BHH. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 1-15 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  56. A comparison of two SIMD implementations of the 2D discrete wavelet transform

    Shahbahrami, A. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 169-177 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. A composable, energy-managed, realtimeMPSOC platform

    Goossens, KGW., Molnos, AM., Ambrose, JA., Nelson, AT., Stefan, RA. & Cotofana, SD., 2010, 12th Intl. optimization electrical and electronic equipment. s.n. (ed.). s.l.: IEEE Society, p. 870-876 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. A control microarchitecture for fault-tolerant quantum computing

    Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  59. A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

    Medeiros, G. C., Bolzani Poehls, L. M., Taouil, M., Luis Vargas, F. & Hamdioui, S., 2018, In : Microelectronics Reliability. 88-90, p. 355-359 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  60. A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

    Cucu Laurenciu, N. & Cotofana, SD., 2013, 21st IFIP/IEEE international conference on very large scale integration. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. A drift-reduced hierarchical wavelet coding scheme for scalable video transmissions

    Choupani, R., Wong, S. & Tolun, MR., 2009, The first international conference on advances in multimedia. Burdescu, DD., Crespi, N. & Dini, O. (eds.). Piscataway: IEEE Society, p. 68-73 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. A dynamic pricing and bidding strategy for autonomous agents in grids

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2007, 6th international joint conference on autonomous agents and multi-agent systems. Joseph S Bergamaschi S, D. Z. (ed.). s.l.: s.l., p. 70-81 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. A dynamically reconfigurable queue scheduler

    Kachris, C. & Vassiliadis, S., 2006, 2006 International conference on Field Programmable Logic and Applications. Koch, A., Leong, P. & Boemo, E. (eds.). Piscataway: IEEE Society, p. 869-872 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. A family of single electron static buffered Boolean logic

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 339-343 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  65. A fast CRC update implementation

    Lu, W. & Wong, JSSM., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 113-120 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. A fault primitive based analysis of dynamic memory faults

    Hamdioui, S., Gaydadjiev, GN. & van de Goor, AJ., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 84-89 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. A fault primitive based analysis of linked faults in RAMs

    Al-Ars, Z., Hamdioui, S. & van de Goor, AJ., 2003, MTDT 2003; Records of the 2003 international workshop on memory technology, design and testing. s.n. (ed.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. A flexible simulator for exploring hardware rasterizers

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  70. A flexible simulator of pipelined processors

    Juurlink, BHH., Bertels, KLM. & Li, B., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 483-493 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. A framework for adaptive matchmaking in distributed computing

    Sigdel, K., Bertels, K., Pourebrahimi, B., Vassiliadis, S. & Shuai, Y., 2005, Proceedings of GRID workshop Cracow-04. Bubak, M., Turala, M. & Wiatr, K. (eds.). Kraków: Cyfronet AGH, p. 150-157 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  73. A full adder implementation using SET based linear threshold gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. Baric, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 665-669 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of a multi-level reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013.

    Research output: Contribution to conferencePosterScientific

  75. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of total reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. A generic digital architecture & compiler for implantable devices

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 69-72 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. A hardware cache memcpy accelerator

    Wong, JSSM., Campos Soares Borrego, F. & Vassiliadis, S., 2006, International Conference on Field Programmable Technology. s.n. (ed.). Piscataway: IEEE Society, p. 141-147 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. A hardware implementation of the unisim pipeline model

    Stefan, RA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 259-263 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. A hardware/software co-simulation environment for graphics accelerator development in ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 255-267 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  80. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2012, Conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. A hierarchical sparse matrix storage format for vector processors

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2003, IPDPS 2003; 17th international parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. A high-level debug environment for communication-centric debug

    Goossens, KGW., Vermeulen, B. & Beyranvand Nejad, A., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 202-207 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

    Nadeem, M., Wong, S., Kuzmanov, GK. & Shabbir, A., 2009, 2009 IEEE/ACM/IFIP 7th workshop on embedded for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 18-27 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. A hybrid cross layer architecture for wireless protocol stacks

    Chang, Z. & Gaydadjiev, GN., 2008, 2008 international wireless communications and mobile computing conference. s.n. (ed.). Piscataway: IEEE Society, p. 279-285 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  87. A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

    Strano, A., Ludovici, D. & Bertozzi, D., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 20-27 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  89. A lightweight speculative and predicative scheme for hardware execution

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 130-141 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  92. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 283-293 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  94. A linear threshold gate implemantation in single electron technology

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. A Jacobs (ed.). Los Alamitos: IEEE, p. 93-98 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. A load/store unit for a memcpy hardware accelerator

    Vassiliadis, S., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 537-541 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  98. A low cost method to tolerate soft errors in the NoC router control plane

    Chen, C. & Cotofana, SD., 2013, 26th Annual IEEE International SoC Conference). s.n. (ed.). Piscataway: IEEE Society, p. 374-379 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. A low power 2D/3D graphics accelerator: The initial design

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2001, S.l.: s.n. 18 p.

    Research output: Book/ReportReportProfessional

  100. A low power 2D/3D graphics accelerator; A preliminary ISA

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 40 p.

    Research output: Book/ReportReportProfessional

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