1. ¿MOS enhanced differential current-switch threshold logic gates

    Li, KC., Padure, MD. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 530-535 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  2. using VLIW softcore processors for image processing applications

    Hoozemans, JJ., Wong, S. & Al-Ars, Z., 2015, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV. Soudris, D. & Carro, L. (eds.). Piscataway: IEEE Society, p. 315-318 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. tQUAD-memory bandwith usage analysis

    Ostadzadeh, SA., Corina, M., Galuzzi, C. & Bertels, KLM., 2010, 39th intl. conf. on parallel processing workshops. s.n. (ed.). Piscataway: IEEE Society, p. 217-226 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. rSesame - a generic system-level runtime simulation framework for reconfigurable architectures

    Sigdel, K., Thompson, M., Galuzzi, C., Pimentel, AD. & Bertels, K., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 460-464 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. pi-VEX: a reconfigurable and extensible softcore VLIW processor

    Wong, S., As van, T. & Brown, G., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. hArtes: Holistic Approach to Reconfigurable Real-Time Embedded Systems

    Kuzmanov, GK., Sima, VM., Bertels, KLM., Coutinho, G., Luk, W., Marchiori, G., Tripiccione, R. & Ferrandi, F., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hübner, M. (eds.). Berlin - Heidelberg: Springer, p. 91-116 290 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  7. eQASM: An executable quantum instruction set architecture

    Fu, X., Riesebos, L., Rol, M. A., Van Straten, J., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., Newsum, V., Loh, K. K. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., Dicarlo, L. & Bertels, K., 2019, Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. Louri, A. & Venkataramani, G. P. (eds.). Piscataway, NJ: IEEE, p. 224-237 14 p. 8675197

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits

    Safiruddin, S., Lefter, M., Borodin, DV., Voicu, GR. & Cotofana, SD., 2012, ACM International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. You can catch more bugs with transaction level honey

    Abramovici, MM., Goossens, KGW., Greenbaum, J., Stollon, N. & Donlin, A., 2008, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 121-124 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Yield improvement for 3D wafer-to-wafer stacked memories

    Taouil, M. & Hamdioui, S., 2012, In : Journal of Electronic Testing: theory and applications. 28, 4, p. 523-534 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Yield improvement and test cost optimization for 3D stacked ICs

    Hamdioui, S. & Taouil, M., 2011, 20th IEEE Asian Test Symposium 2011. Chatterjee, A., Patra, A., Kundu, S. & Ravi, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 480-485 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Yield and cost analysis or 3D stacked ICs

    Taouil, M., 2014, 215 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  13. Yield Improvement for 3D wafer-to-wafer stacked ICs using wafer matching

    Taouil, M., Hamdioui, S. & Marinissen, EJ., 2015, In : ACM Transactions on Design Automation of Electronic Systems. 20, 2, p. 1-23 23 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Y'UV-to-R'G'B' color space conversion on FPGA-augmented TriMedia-32 processor

    Sima, M., Vassiliadis, S., van Eijndhoven, JTJ. & Cotofana, SD., 2002, Proceeding ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 465-471 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. Wrapper design for the reuse of networks-on-chip as test access mechanism

    Amory, A., Goossens, KGW. & Marinissen, E., 2006, Proc. European Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 213-218 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

    Amory, A., Goossens, KGW., Marinissen, E., Lubaszewski, M. & Moraes, F., 2007, In : IET Computers and Digital Techniques. 1, 3, p. 197-206 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Worst-case bit line coupling backgrounds for open defects in SRAM cells

    Irobi, IS. & Al-Ars, Z., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 25-30 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. Wireless SDR solutions: The challenge and promise of next generation handsets

    Glossner, CJ., Hokenek, E. & Moudgill, M., 2002, CDC 2002 Communications Design Conference Proceedings. CMP Media LLC, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. Why is CMOS scaling coming to an END?

    Haron, NZB. & Hamdioui, S., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 98-103 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Weighted embedded zero tree for scalable vidoe compression

    Choupani, R., Wong, S. & Tolun, MR., 2008, Proceedings of the 2008 international conference on image processing, computer vision, & pattern recognition. Arabnia, HR. (ed.). USA: CSREA Press, p. 681-684 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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