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  1. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  2. A low-power multithreaded processor for baseband communication systems

    Schulte, M., Glossner, CJ., Mamidi, S., Moudgill, M. & Vassiliadis, S., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 393-402 10 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A low-power carry skip adder with fast saturation

    Schulte, MJ., Chirca, K., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 269-279 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A low-cost, power-efficient texture cache architecture

    Antochi, I., Juurlink, BHH. & Cilio, AGM., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 250-257 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A low-cost BRAM-Based function reuse for configurable soft-core processors in FPGAs

    Becker, P. H. E., Sartor, A. L., Brandalero, M., Trevisan Jost, T., Wong, S., Carro, L. & Beck, A. C., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer, p. 499-510 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A low power 2D/3D graphics accelerator; A preliminary ISA

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 40 p.

    Research output: Book/ReportReportProfessional

  8. A low power 2D/3D graphics accelerator: The initial design

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2001, S.l.: s.n. 18 p.

    Research output: Book/ReportReportProfessional

  9. A low cost method to tolerate soft errors in the NoC router control plane

    Chen, C. & Cotofana, SD., 2013, 26th Annual IEEE International SoC Conference). s.n. (ed.). Piscataway: IEEE Society, p. 374-379 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

ID: 19943