1491 - 1500 out of 1,593Page size: 10
  1. The recursive grid layout scheme for VLSI layout of hierarchical networks

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999 Proceedings. Los Alamitos: IEEE, p. 441-445 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  2. The sandblaster automatic multithreaed vectorizing compiler

    Jinturkar, S., Glossner, CJ., Kotlyar, V. & Moudgill, M., 2004, CD Proceedings at the 2004 Global Signal Processing Expo (GSPx) and International Signal Processing Conference (ISPC). Newton: Global Technology Conferences, p. 1-17 17 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. The scalable networking scheme for high-speed networks

    Yeh, CH. & Varvarigos, EA., 2000, ICC 2000 conference record: global convergence through communications. Piscataway: IEEE Society, p. 1335-1342 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. The spiral search: a linear complexity algorithm for the generation of convex MIMO instruction-set extensions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, ICFPT 2007. Takeshi Ikenaga Hideharu Amano, A. Y. (ed.). s.l., p. 337-340 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. The state-of-art future trends in testing embedded memories

    Hamdioui, S., Gaydadjiev, GN. & van de Goor, AJ., 2004, Records of the 2004 International workshop on Memory Technology, Design and Testing MTDT 2004. Titsworth, FM. (ed.). Piscataway: IEEE, p. 54-59 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. The synchronization challenge

    Bertozzi, D., Strano, A., Ludovici, D. & Pavlidis, V., 2010, Designing network-on-chip architectures in the nanoscale era. Flich, J. & Bertozzi, D. (eds.). s.l.: s.n., p. 176-233 57 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  7. The universal multiplier unit

    Calderón, H. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 341-346 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. Threshold logic parallel counters for 32-bit multipliers

    Celinski, P., Cotofana, SD. & Abbott, D., 2002, International symposium on smart materials, Nano-, and micro-smart systems 2002. s.n. (ed.). Belingham: SPIE, p. 205-214 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Through testing of any multiport memory with linear tests

    Hamdioui, S. & van de Goor, AJ., 2002, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 21, 2, p. 217-232 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Throughput analysis and voltage-frequency island partitioning for streaming applications under process variation

    Mirzoyan, D., Stuijk, S., Akesson, B. & Goossens, KGW., 2013, Proceedings 2013 IEEE 11th Symposium on Embedded Systems for Real-Time Multimedia. Stefanov, T. & Palesi et al, M. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

ID: 19943