1491 - 1500 out of 1,563Page size: 10
  1. Towards the utilization of reconfigurable processors in grid networks

    Nadeem, MF., Anjam, F., Ostadzadeh, SA., Ahmadi, M. & Wong, JSSM., 2010, Prorisc 2010. s.n. (ed.). Nederland: STW, p. 29-35 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Towards variation-aware system-level power estimation of DRAMs: an empirical approach

    Chandrasekar, K., Weis, C., Akesson, B., Wehn, N. & Goossens, KGW., 2013, 50th Design Automation Conference. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Trade offs in the design of a router with guaranteed and best-effort services for networks on chip

    Rijpkema, E., Goossens, KGW., Radulescu, A. & Dielissen, J., 2008, Design, Automation, and Test in Europe. Lauwereins, R. & Madsen, J. (eds.). Heidelberg: Springer, p. 125-139 515 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  4. Trade-offs between voltage scaling and processor shutdown for low-energy embedded multiprocessors

    de Langen, PJ. & Juurlink, B., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 75-85 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Trade-offs in the configuration of a network on chip for multiple use-cases

    Hansson, A. & Goossens, KGW., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Trading efficiency for energy in a texture cache architecture

    Antochi, I., Juurlink, BHH., Cilio, AGM. & Liuha, P., 2002, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. Transaction-based communication-centric debug

    Goossens, KGW., Vermeulen, B., van Steeden, R. & Bennebroek, M., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Transforming and parallelizing ANSI C programs using pattern recognition

    Boekhold, M., Karkowski, I. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 673-682 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Transition Fault Testing for Offline Adaptive Voltage Scaling

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2017, p. 1-1. 1 p.

    Research output: Contribution to conferencePosterScientific

  10. Transmission channel noise aware energy effective LDPC decoding

    Marconi, T., Spagnol, C., Popovici, E. & Cotofana, SD., 2015, 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration: Revised and extended selected papers. Sanz-Pascual, MT., Claesen, L., Reis, R. & Sarmiento-Reyes, A. (eds.). Cham: Springer, p. 198-219 22 p. (IFIP Advances in Information and Communication Technologies; vol. 464).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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