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  1. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A linear threshold gate implemantation in single electron technology

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. A Jacobs (ed.). Los Alamitos: IEEE, p. 93-98 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 283-293 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 130-141 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. A lightweight speculative and predicative scheme for hardware execution

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  9. A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

    Strano, A., Ludovici, D. & Bertozzi, D., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 20-27 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

ID: 19943