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  1. A generic digital architecture & compiler for implantable devices

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 69-72 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of total reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of a multi-level reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013.

    Research output: Contribution to conferencePosterScientific

  4. A full adder implementation using SET based linear threshold gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. Baric, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 665-669 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A framework for adaptive matchmaking in distributed computing

    Sigdel, K., Bertels, K., Pourebrahimi, B., Vassiliadis, S. & Shuai, Y., 2005, Proceedings of GRID workshop Cracow-04. Bubak, M., Turala, M. & Wiatr, K. (eds.). Kraków: Cyfronet AGH, p. 150-157 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A flexible simulator of pipelined processors

    Juurlink, BHH., Bertels, KLM. & Li, B., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 483-493 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A flexible simulator for exploring hardware rasterizers

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A fault primitive based analysis of linked faults in RAMs

    Al-Ars, Z., Hamdioui, S. & van de Goor, AJ., 2003, MTDT 2003; Records of the 2003 international workshop on memory technology, design and testing. s.n. (ed.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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