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  1. A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2011, Proceedings 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 818-822 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

    Yang, B., Popovici, E., Quille, M. A., Amann, A. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 79-84 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A Sparse VLIW Instruction Encoding Scheme Compatible with Generic Binaries

    Brandon, A., Hoozemans, J., van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck Filho, A. C. & Wong, S., Jan 2016. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  6. A Simulation Framework for Reconfigurable Processors in Large-scale Distributed Systems

    Nadeem, MF., Ostadzadeh, SA., Nadeem, M., Wong, JSSM. & Bertels, KLM., 2011, International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Sheu, JP. & Wang, CL. (eds.). Piscataway: IEEE Society, p. 352-360 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A Security Verification Template to Assess Cache Architecture Vulnerabilities

    Ghasempouri, T., Raik, J., Paul, K., Reinbrecht, C., Hamdioui, S. & Taouil, M., 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): Proceedings. IEEE, p. 1-6 6 p. 9095707

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A Reconfigurable Audio Beamforming Multi-Core Processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Symposium on Applied Reconfigurable Computing. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R. & El-Ghazawi, T. (eds.). Heidelberg: Springer, p. 3-14 12 p. (Lecture Notes in Computer Science; vol. 6578).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A Novel Virtual Age Reliability Model for Time-toFailure Prediction

    Wang, Y. & Cotofana, SD., 2010, IEEE International Integrated Reliability Workshop Final Report. Young, C. & Geilenkeuser, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 102-105 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit

    Weller, D. D., Erozan, A. T., Rasheed, F., Bishnoi, R., Aghassi-Hagmann, J. & Tahoori, M. B., 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 6, p. 1496-1504 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

ID: 19943