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  1. A Novel Dynamic Task Scheduling Algorithm for Grid Networks with Reconfigurable Processors

    Nadeem, MF., Ostadzadeh, SA., Ahmadi, M., Nadeem, M. & Wong, JSSM., 2011, 5th HiPEAC Workshop on Reconfigurable Computing. s.n. (ed.). s.l.: HiPEAC, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A Non-Intrusive Online FPGA Test Scheme Using A Hardwired Network on Chip

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 351-359 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A Microarchitecture for a Superconducting Quantum Processor

    Fu, X., Rol, M. A., Bultink, C. C., van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., Almudéver, C. G., DiCarlo, L. & Bertels, K., 2018, In : IEEE Micro. 38, 3, p. 40-47 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A Locality-Aware Hash-Join Algorithm

    Fang, J., Hidders, J., Bertels, K., Lee, J. & Hofstee, P., 2016, p. 1-4. 4 p.

    Research output: Contribution to conferenceAbstractScientific

  7. A Java-enabled DSP

    Glossner, CJ., Schulte, MJ. & Vassiliadis, S., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 307-327 19 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  8. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A Heterogeneous Quantum Computer Architecture

    Fu, X., Riesebos, L., Lao, L., García Almudever, C., Sebastiano, F., Versluis, R., Charbon, E. & Bertels, K., 2016, Proceedings of the ACM International Conference on Computing Frontiers, CF '16. New York: Association for Computing Machinery (ACM), p. 323-330 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model

    Fang, J., Chen, J., Lee, J., Al-Ars, Z. & Hofstee, P., 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): Proceedings. IEEE, p. 335-335 1 p. 8735518

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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