1. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of total reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  2. A generic digital architecture & compiler for implantable devices

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 69-72 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. A hardware cache memcpy accelerator

    Wong, JSSM., Campos Soares Borrego, F. & Vassiliadis, S., 2006, International Conference on Field Programmable Technology. s.n. (ed.). Piscataway: IEEE Society, p. 141-147 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. A hardware implementation of the unisim pipeline model

    Stefan, RA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 259-263 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. A hardware/software co-simulation environment for graphics accelerator development in ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 255-267 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  6. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2012, Conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. A hierarchical sparse matrix storage format for vector processors

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2003, IPDPS 2003; 17th international parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. A high-level debug environment for communication-centric debug

    Goossens, KGW., Vermeulen, B. & Beyranvand Nejad, A., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 202-207 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

    Nadeem, M., Wong, S., Kuzmanov, GK. & Shabbir, A., 2009, 2009 IEEE/ACM/IFIP 7th workshop on embedded for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 18-27 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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