101 - 200 out of 1,585Page size: 100
  1. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A low-cost, power-efficient texture cache architecture

    Antochi, I., Juurlink, BHH. & Cilio, AGM., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 250-257 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A low-power carry skip adder with fast saturation

    Schulte, MJ., Chirca, K., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 269-279 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A low-power multithreaded processor for baseband communication systems

    Schulte, M., Glossner, CJ., Mamidi, S., Moudgill, M. & Vassiliadis, S., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 393-402 10 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A low-power threshold logic family

    Padure, MD., Cotofana, SD., Vassiliadis, S., Dan, C. & Bodea, M., 2002, ICECS 2002; 9th IEEE International Conference on Electronica, Circuits and Systems. Piscatawy, NJ. USA: IEEE Society, p. 657-660 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A mathematical game and its applications to the design of interconnection networks

    Yeh, CH. & Varvarigos, EA., 2001, Proceedings. Los Alamitos: IEEE, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A matrix-multiply unit for posits in reconfigurable logic leveraging (Open)CAPI

    Chen, J., Al-Ars, Z. & Hofstee, H. P., 2018, Proceedings of the Conference for Next Generation Arithmetic, CoNGA 2018. Association for Computing Machinery (ACM), p. 1-5 5 p. 1

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A memcpy hardware accelarator solution for non cache-line aligned copies

    Campos Soares Borrego, F. & Wong, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 397-402 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A memory-optimized bloom filter using an additional hashing function

    Ahmadi, M. & Wong, S., 2008, IEEE GLOBECOM 2008. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. A method and system for power management

    Molnos, AM. & Goossens, KGW., 2013, Patent No. US 8569911 B2, Priority date 29 Oct 2013

    Research output: Patent

  12. A method and system for power management

    Molnos, AM. & Goossens, KGW., 2009, Patent No. WO 2009125371 A2, Priority date 15 Oct 2009

    Research output: Patent

  13. A method to analyze the fault tolerance of molecular quantum-dot cellular automata systems

    Milosavljevic, D. & Cotofana, SD., 2006, Proceedings 2006 International Semiconductor conference. s.n. (ed.). Piscataway: IEEE Society, p. 399-402 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. A minimalistic for reconfigurable WFS-based immersive-audio

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, 2010 Intl. conf. on reconfigurable computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. A modified merging approach for datapath configuration time reduction

    Fazlali, M., 2010, Reconfigurable computing: architectures, tools and applications. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 318-328 11 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2006, Proc. Euromicro Symposium on Digital System Design. s.n. (ed.). Piscataway: IEEE Society, p. 97-104 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. A multiported register file with register renaming for configurable softcore VLIW processors

    Anjam, F., Wong, JSSM. & Nadeem, MF., 2010, 2010 Intl. conf. on field programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A multipurpose clustering algorithm for task partitioning in multicore reconfigurable systems

    Ostadzadeh, SA., Meeuws, RJ., Sigdel, K. & Bertels, K., 2009, The international conference on complex, intelligent and software intensive systems. s.n. (ed.). Piscataway: IEEE Society, p. 663-668 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  23. A new approach to implement discrete wavelet transform using collaboration of reconfigurable elements

    Shahbahrami, A., Ahmadi, M., Wong, S. & Bertels, K., 2009, 2009 intl. conf. on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 344-349 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. A new digital architecture for reliable, ultra-low-power systems

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 350-355 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A new latch-based threshold logic familiy

    Padure, MD., Cotofana, SD., Dan, C., Bodea, M. & Vassiliadis, S., 2001, CAS 2001: proceedings. Piscataway: IEEE Society, p. 531-534 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. A new model of placement quality measurement for online task placement

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 307-310 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. A novel HDL coding style to reduce power consumption for reconfigurable devices

    Thomas, TM., Theodoropoulos, D., Bertels, KLM. & Gaydadjiev, GN., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 295-299 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. A novel approach for accelerating the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z. & Nawaz, Z., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 40-45 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

    Thomas, TM., Hur, JY., Bertels, K. & Gaydadjiev, GN., 2010, 2010 IEEE 8th symp. on application specific processors. s.n. (ed.). CA, USA: IEEE Society, p. 105-110 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. A novel fast online placement algorithm on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 296-299 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. A novel flit serialization strategy to utilize partially faulty links in networks-on-chip

    Chen, C. & Lu, Y., 2012, 2012 Sixth IEEE/ACM international symposium on networks-on-chip. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. A novel productivity-driven logic element for field-programmable devices

    Marconi, T., Bertels, KLM. & Gaydadjiev, GN., 2014, In : International Journal of Electronics. 101, 6, p. 731-762 32 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. A padding processor for MPEG-4

    Kuzmanov, G., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 470-474 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. A parallel FPGA design of the Smith-waterman traceback

    Nawaz, Z., Nadeem, M., van Someren, J. & Bertels, KLM., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 454-459 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. A partially buffered crossbar packet switching architecture and its scheduling

    Mhamdi, LL., 2008, IEEE Intl. Symposium on Computers and Communications. s.n. (ed.). s.l.: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. A peer-to-peer agent auction

    Ogston, EFYL. & Vassiliadis, S., 2002, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part I. Castelfranchi, C. & Johnson, WL. (eds.). New York: Association for Computing Machinery (ACM), p. 151-159 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. A performance model for network processor architectures in packet processing system

    Ahmadi, M. & Wong, S., 2007, 19th IASTED Parallel and distributed computing and systems. Zheng SQ (ed.). Anaheim: ACTA Press, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. A platform for RFID security and privacy administration

    Rieback, M., Gaydadjiev, GN., Crispo, B., Hofman, R. F. H. & Tanenbaum, AS., 2006, Proc. 20th Large Installation System Administration Conf.. s.n. (ed.). Berkeley, USA: USENIX, p. 89-102 14 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. A polymorphic register file for matrix operations

    Ciobanu, CB., Kuzmanov, GK., Gaydadjiev, GN. & Ramirez, A., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 241-249 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. A power aware HW/SW partitioning for a DVB-H receiver module

    Koryfides, I., Cotofana, SD. & van Gassel, J., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 293-299 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. A practical scheduler for high-speed packet switches and internet routers

    Mhamdi, LL. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 398-403 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  43. A pragmatic gaze on stochastic resonance based variability tolerant memristance enhancement

    Ntinas, V., Rubio, A., Sirakoulis, G. C. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. 5 p. 8702792

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. A predictor-based power-saving policy for DRAM memories

    Thomas, G., Chandrasekar, K., Akesson, B., Juurlink, BHH. & Goossens, KGW., 2012, 15th Euromicro conference on digital system design. s.n. (ed.). s.n.: Euromicro, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. A profiling framework for design space exploration in heterogeneous systems context

    Sigdel, K., Meeuws, RJ. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 363-368 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. A proposal of a tile-based open GL compliant rasterization engine

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 123 p.

    Research output: Book/ReportReportProfessional

  48. A quantative prediction model for hardware/software partitioning

    Meeuws, RJ., Yankova, YD., Bertels, K., Gaydadjiev, GN. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 735-739 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. A reconfigurable baseband for 2.5G/3G and beyond

    Glossner, CJ., Iancu, D., Hokenek, E. & Moudgill, M., 2003, WWC'2003 Proceedings; proceedings of 2003 world wireless congress. s.n. (ed.). San Francisco: Delson Group Inc., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  50. A reconfigurable beamformer for audio applications

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 2009 IEEE 7th symposium on application specific processors. s.n. (ed.). Piscataway: IEEE Society, p. 80-87 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. A reconfigurable functional unit for TriMedia/CPU64

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliads, S. (eds.). Berlin: Springer, p. 224-242 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  52. A reconfigurable hardware based embedded scheduler for buffered crossbar switches

    Mhamdi, L., Kachris, C. & Vassiliadis, S., 2006, Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 143-149 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. A reconfigurable perfect-hashing scheme for packet inspection

    Sourdis, I., Pnevmatikatos, DN., Wong, JSSM. & Vassiliadis, S., 2005, Proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005). Rissa, T., Wilton, S. & Leong, P. (eds.). IEEE Society, p. 644-647 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. A reconfigurable platform for multi-service edge routers

    Kachris, C. & Vassiliadis, S., 2007, 20th Symposium on integrated circuits and systems design. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 165-169 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. A reverse converter for the new 4-moduli set {2n+3, 2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international conference on electronics circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 113-116 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. A run-time modulo scheduling by using a binary translation mechanism

    Ferreira, R., Denver, W., Pereira, M., Quadros, J., Carro, L. & Wong, S., 2014, Proceedings - 2014 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Galuzzi, C. & Veidenbaum, AV. (eds.). Piscataway, NJ, USA: IEEE Society, p. 75-82 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. A run-time task migration scheme for an adjustable issue-slots multi-core processor

    Anjam, F., Kong, Q., Seedorf, RAE. & Wong, JSSM., 2012, 8th International symposium on applied reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme

    Berekovic, M. & Niggemeier, T., 2006, Embedded Computer Systems: Architectures, Modeling, and Simulation. Vassiliadis, S., Wong, S. & Hamalainen, TD. (eds.). Heidelberg: Springer, p. 289-298 10 p. (Lecture Notes in Computer Science; vol. 4017).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

    Lefter, M., Voicu, GR. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 425-428 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. A shared reconfigurable VLIW multiprocessor system

    Anjam, F., Wong, S. & Nadeem, MF., 2010, IPDPS 2010 conf. 24th IEEE intl. parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. A sign bit only phase normalization for rotation and scale invariant template matching

    Ma, M., van Genderen, AJ. & Beukelman, P., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 641-646 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  64. A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, 19th IEEE International conference on embedded and real-time computing systems and applications. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. A software-defined communications baseband design

    Glossner, CJ., Iancu, D., Lu, J., Hokenck, E. & Moudgill, M., 2003, In : IEEE Communications Magazine. 41, 1, p. 4-12 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  66. A sparse VLIW instruction encoding scheme compatible with generic binaries

    Brandon, A., Hoozemans, J., Van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck, A. C. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers (IEEE), 7 p. 7393361

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. A static low-power, high-peformance 32-bit carry skip adder

    Chirca, K., Schulte, M., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, Architectures, methods and tools. Selvaraj, H. (ed.). Piscataway: IEEE, p. 615-619 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. A sum of absolute differences implementation in FPGA hardware

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, EUROMICRO 2002; Proceedings of the 28th EUROMICRO Conference. Fernandez, M. (ed.). Piscataway, NJ. USA: IEEE Society, p. 183-188 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. A survey of autonomic computing systems

    Nami, MR. & Bertels, K., 2007, The third international conference on autonomic and autonomous systems. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. A survey of coarse-grain reconfigurable architectures and CAD tools

    Theodoridis, G., Soudris, D. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 89-152 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  71. A survey of peer-to-peer networks

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2005, Proceedings of the SAFE & ProRISC 2005. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 570-577 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. A survey on low-power techniques for single and multicore systems

    Zandrahimi, M. & Al-Ars, Z., 2014, Proceedings 3rd International Conference on Context-Aware Systems and Applications. Mansoor, W., Maamar, Z. & Rabhi, F. (eds.). Ghent, Belgium: EAI, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

    van de Goor, AJ. & Tlili, IBS., 2003, In : IEEE Transactions on Computers. 52, 10, p. 1320-1330 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. A systolic architecture for the Smith-Waterman algorithm with high performance cell design

    Hasan, L., Khawaya, YM. & Bais, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 35-42 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. A taxonomy of custom computing machines

    Sima, M., Vassiliadis, S., Cotofana, SD., van Eijndhoven, JTJ. & Vissers, K., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 71-77 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  76. A taxonomy of field-programmable custom computing machines

    Sima, M., Vassiliadis, S. & Cotofana, SD., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 299-378 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  77. A turnstile based single electron memory element

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, SAFE 2001: proceedings. Utrecht: STW Technology Foundation, p. 103-108 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. A two-phase practical parallel algorithm for construction of huffman codes

    Ostadzadeh, SA., Maryam Elahi, B., Tabrizi, ZZ., Amir Moulavi, M. & Bertels, K., 2007, 2007 intl. conf. on Parallel and distributed processing techniques and applicationss. Arabnia HR (ed.). USA: CSREA Press, p. 284-291 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. A unified addition structure for moduli set 2n-1, 2n, 2n+1 based on a novel RNS representation

    Timarchi, S., Fazlali, M. & Cotofana, SD., 2010, ICCD 2010. s.n. (ed.). Piscataway: IEEE Society, p. 247-252 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. A unified execution model for multiple computation models of streaming applications on a composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, In : Journal of Systems Architecture. 59, 10, part C, p. 1032-1046 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. A user-level library for fault tolerance on shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 15th IEEE symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  83. A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

    Celinski, P., Cotofana, SD. & Abbott, D., 2003, Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 73-80 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors

    Mei, B., Berekovic, M. & Mignolet, J-Y., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 255-298 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  85. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

    Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 61-73 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  86. ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications

    Al-Ars, Z., van der Vlugt, S., Jääskeläinen, P. & van der Linden, F., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 1-7 7 p.

    Research output: Contribution to journalEditorialScientificpeer-review

  87. ALU Augmentation for MPEG-4 repetitive padding

    Kuzmanov, GK. & Vassiliadis, S., 2002, MPCS'02 Proceedings of the 2002 Euromicro conference on Massively-Parallel Computing Systems. Fort Collins, Col. USA: National Technological University Press, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  88. Accelarating color space conversion using extended subwords and the matrix register file

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2006, Eighth IEEE international Symposium on multimedia. Piscataway: IEEE Society, p. 37-44 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Accelerating DNA Variant Calling Algorithms on High Performance Computing Systems

    Ren, S., 2018, 83 p.

    Research output: ThesisDissertation (TU Delft)

  90. Accelerating a geometrical approximated PCA algorithm using AVX2 and CUDA

    Machidon, A. L., Machidon, O. M., Ciobanu, C. B. & Ogrutan, P. L., 2020, In : Remote Sensing. 12, 12, 29 p., 1918.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Accelerating complex brain-model simulations on GPU platforms

    Nguyen, HAD., Al-Ars, Z., Smaragdos, G. & Strydis, C., 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ, USA: IEEE Society, p. 974-979 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Accelerating the secure remote password protocol using reconfigurable hardware

    Groen, PT., Hämäläinen, P., Juurlink, BHH. & Hämäläinen, T., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 471-480 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. Acceleration of Bioinformatics Sequence Alignment - A Hardware Perspective

    Hasan, L., 2011, Germany: LAP LAMBERT Academic Publishing. 132 p.

    Research output: Book/ReportBookScientific

  94. Acceleration of Smith-Waterman using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Acceleration of biological sequence alignment using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 233-237 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

    Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Achieving fanout capabilities in single electron encoded logic networks

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 2. Piscataway: IEEE Society, p. 1383-1386 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

    Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

    Research output: Contribution to journalArticleScientificpeer-review

  99. Adapting communication for adaptable processors: a multi-axis reconfiguration approach

    Santos, PC., Nazar, GL., Anjam, F. & Wong, JSSM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs

    Monteiro OliveiraCortez, AM., van der Leest, V., Maes, R., Schrijen, GJ. & Hamdioui, S., 2013, IEEE International symposium on hardware-oriented security and trust. s.n. (ed.). Piscataway: IEEE Society, p. 35-40 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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