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  1. Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V

    Fritzmann, T., Sharif, U., Müller-Gritschneder, D., Reinbrecht, C., Schlichtmann, U. & Sepulveda, J., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings . IEEE, p. 1148-1153 6 p. 8715173

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Towards Robust Implementation of Memristor Crossbar Logic Circuits

    Xie, L., 2016, 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). Piscataway., NJ: IEEE, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Towards a Scalable Quantum Computer

    Almudever, C. G., Khammassi, N., Hutin, L., Vinet, M., Babaie, M., Sebastiano, F., Charbon, E. & Bertels, K., 2018, Proceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018. Piscataway, NJ: IEEE, 1 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Towards a runtime system for reconfigurable computers: a virtualization approach

    Sabeghi, M. & Bertels, K., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 1576-1579 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Towards an effective utilization of partially defected interconnections in 2D mesh NoCs

    Chen, C. & Cotofana, SD., 2014, Proceedings - 2014 IEEE Computer Society Annual Symposium on VLSI. Mohanty, SP., Ranganathan, N. & Bhanja, S. (eds.). Los Alamitos, CA, USA: IEEE, p. 492-497 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Towards code safety with high performance

    Nazarian, G., Carro, L. & Gaydadjiev, GN., 2014, Architecture of Computing Systems - Proceedings 27th International Conference on Architecture of Computing Systems. Maehle, E., Römer, K., Karl, W. & Tovar, E. (eds.). Cham, Switzerland: Springer, p. 209-220 12 p. (Lecture Notes in Computer Science; vol. 8350).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Towards energy effective LDPC decoding by exploiting channel noise variability

    Marconi, T., Spagnol, C., Popovici, E. & Cotofana, SD., 2014, Proceedings - 2014 22nd International Conference on Very Large Scale Integration. Garcia, L. (ed.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

    Voicu, GR. & Cotofana, SD., 2013, 9th ACM/IEEE International Symposium on Nanoscale Architectures). s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Towards system level runtime design space exploration of reconfigurable architectures

    Sigdel, K., Thompson, M., Pimentel, A. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 100-107 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Towards the additional use of phase processing in multistatic FMCW radar, considerations and experimental results

    Swart, PJF., Steenstra, HT., Muller, FL., van der Zwan, WF., van Genderen, P., Ligthart, LP., Reijns, GL. & van Gemund, AJC., 1999, Conference proceedings. Vol. 1. London: Microwave Engineering Europe, p. 238-241 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Towards the performace analysis of reconfigurable hardwares in grid networks

    Ahmadi, M. & Nadeem, MF., 2010, 23rd Canadian conf. on electrical and computer engineering. s.n. (ed.). Los Alamitos, CA: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Towards the utilization of reconfigurable processors in grid networks

    Nadeem, MF., Anjam, F., Ostadzadeh, SA., Ahmadi, M. & Wong, JSSM., 2010, Prorisc 2010. s.n. (ed.). Nederland: STW, p. 29-35 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Towards variation-aware system-level power estimation of DRAMs: an empirical approach

    Chandrasekar, K., Weis, C., Akesson, B., Wehn, N. & Goossens, KGW., 2013, 50th Design Automation Conference. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Trade offs in the design of a router with guaranteed and best-effort services for networks on chip

    Rijpkema, E., Goossens, KGW., Radulescu, A. & Dielissen, J., 2008, Design, Automation, and Test in Europe. Lauwereins, R. & Madsen, J. (eds.). Heidelberg: Springer, p. 125-139 515 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  15. Trade-offs between voltage scaling and processor shutdown for low-energy embedded multiprocessors

    de Langen, PJ. & Juurlink, B., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 75-85 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Trade-offs in the configuration of a network on chip for multiple use-cases

    Hansson, A. & Goossens, KGW., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Trading efficiency for energy in a texture cache architecture

    Antochi, I., Juurlink, BHH., Cilio, AGM. & Liuha, P., 2002, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  18. Transaction-based communication-centric debug

    Goossens, KGW., Vermeulen, B., van Steeden, R. & Bennebroek, M., 2007, First international Symposium on Network-on-Chip. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Transforming and parallelizing ANSI C programs using pattern recognition

    Boekhold, M., Karkowski, I. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 673-682 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Transition Fault Testing for Offline Adaptive Voltage Scaling

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2017, p. 1-1. 1 p.

    Research output: Contribution to conferencePosterScientific

  21. Transmission channel noise aware energy effective LDPC decoding

    Marconi, T., Spagnol, C., Popovici, E. & Cotofana, SD., 2015, 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration: Revised and extended selected papers. Sanz-Pascual, MT., Claesen, L., Reis, R. & Sarmiento-Reyes, A. (eds.). Cham: Springer, p. 198-219 22 p. (IFIP Advances in Information and Communication Technologies; vol. 464).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Transparent reconfigurable acceleration for heterogeneous embedded applications

    Schneider Beck, AC., Rutzig, MB., Gaydadjiev, GN. & Carro, L., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1208-1213 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Transposition mechanism for sparse matrices on vector processors

    Stathis, P., Vassiliadis, S. & Cotofana, SD., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 641-645 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Trends and challenges of SRAM reliability in the nano-scale era

    Seyab, MSK. & Hamdioui, S., 2010, 2010 intl. conf. on design & technology of integrated systems in nanoscale Era. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Trends in low power handset software defined radio

    Glossner, CJ., Iancu, D., Moudgill, M., Schulte, M. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 313-321 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Trends in low power handset software defined radios

    Raja, T. & Glossner, CJ., 2006, 2006 Software Defined Radio Technical Conference and Product Exposition. s.n. (ed.). USA: s.l., p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Trends in tests and failure mechanisms in deep sub-micron technologies

    Hamdioui, S., Al-Ars, Z., Mhamdi, LL., Gaydadjiev, GN. & Vassiliadis, S., 2006, 2006 International conference on Design & Test of Integrated Systems in Nanoscale Technology. Girard, P., Masmoudi, M., Mouine, J. & Renovell, M. (eds.). Piscataway: IEEE Society, p. 216-221 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Two algorithms for the generation of convex MIMO instructions

    Galuzzi, C., Moscu Panainte, E., Bertels, KLM. & Vassiliadis, S., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 260-265 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Two-dimensional memory implementation with multiple data patterns

    Vitkovskiy, A., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 185-190 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Tydi: an open specification for complex data structures over hardware streams

    Peltenburg, J. W., Brobbel, M., Van Straten, J., Al-Ars, Z. & Hofstee, P., 2020, In : IEEE Micro. 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  31. USB enabled PDP8 computer

    van de Pol, J., Mul, MP., Gaydadjiev, GN. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 112-117 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  32. Ultra low power NEMFET based logic

    Enachescu, M., Lefter, M., Bazigos, A., Ionescu, A. & Cotofana, SD., 2013, IEEE International symposium on circuits and systems. Piscataway: IEEE Society, p. 566-569 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

    Makosiej, A., Gupta, N., Vakul, N., Vladimirescu, A., Cotofana, S., Mahapatra, S., Amara, A. & Anghel, C., 2016, In : Micro and Nano Letters. 11, 12, p. 828-831 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. Unbalanced multiple description wavelet coding for scalable video transmission

    Choupani, R., Wong, JSSM. & Tolun, MR., 2012, In : Journal of Electronic Imaging. 21, 4, p. 1-11 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  35. Understanding MPSoCs: Exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

    Sepulveda, J., Reinbrecht, C., Azad, S. P., Niazmand, B. & Jervan, G., 15 Jul 2018, Proceedings - 2018 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2018. Mudge, T. & Pnevmatikatos, D. N. (eds.). New York: Association for Computing Machinery (ACM), p. 162-166 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Undisrupted quality-of-service during reconfiguration on multiple applications in networks on chip

    Hansson, A., Coenen, M. & Goossens, KGW., 2007, Design, Automation & Test in Europe. s.n. (ed.). s.l.: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Unified dual data caches

    Juurlink, BHH., 2003, DSD 2003; euromicro symposium on digital system design, architectures, methodes and tools. s.n. (ed.). Piscataway: IEEE Society, p. 33-41 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Universal Processor Architecture for Biomedical Implants: The SiMS Project

    Strydis, C., 2011, 315 p.

    Research output: ThesisDissertation (TU Delft)

  39. Unstructured agent matchmaking: experiments in timing and fuzzy matching

    Ogston, EFYL. & Vassiliadis, S., 2002, Applied computing 2002: Proceedings of the 2002 ACM symposium on applied computing. New York: Association for Computing Machinery (ACM), p. 300-306 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  40. Untestable faults identification in GPGPUs for safety-critical applications

    Condia, J. E. R., Da Silva, F. A., Hamdioui, S., Sauer, C. & Reorda, M. S., 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers (IEEE), p. 570-573 4 p. 8964677

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Using 3D-COSTAR for 2.5D test cost optimization

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2013, IEEE International 3D Systems Integration Conference. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Using RRNS codes for cluster faults tolerance in hybrid memories

    Haron, NZB. & Hamdioui, S., 2009, 2009 IEEE international symposium on defect and fault tolerance in VLSI systems. Gizopoulos, D., Tehranipoor, M. & Tragoudas, S. (eds.). Piscataway: IEEE Society, p. 85-93 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Using Transition Fault Test Patterns for Cost Effective Offline Performance Estimation

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2017, 2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS). Danvers: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Using a CISC microcontroller to test embedded memories

    van de Goor, AJ., Hamdioui, S. & Gaydadjiev, GN., 2010, IEEE intl. symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 382-387 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Using a Polymorphic VLIW Processor to Improve Schedulability and Performance for Mixed-criticality Systems

    Hoozemans, J., van Straten, J. & Wong, S., Aug 2017, 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Danvers: IEEE, p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Using linear tests for transient faults in DRAMs

    Al-Ars, Z., Hamdioui, S. & Gaydadjiev, GN., 2006, International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

    Mariani, GS., Sima, VM., Palermo, G., Zaccaria, V., Silvano, C. & Bertels, KLM., 2012, Design, automation & test in Europe conference & exhibition. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Using wavelet transform self-similarity for effective multiple description video coding

    Choupani, R., Wong, S. & Tolun, M., 2016, 10th International Conference on Information, Communications and Signal Processing, ICICS 2015. Piscataway, NJ: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. VASILE: a reconfigurable vector architecture for instruction level frequency scaling

    Petrica, L., Codreanu, V. & Cotofana, SD., 2013, 12th IEEE low voltage low power conference. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

    Hoozemans, J., Heij, R., van Straten, J. & Al-Ars, Z., 2017, Applied Reconfigurable Computing: 13th International Symposium, ARC 2017. Wong, S., Beck, A. C., Bertels, K. & Carro, L. (eds.). Cham: Springer, p. 36-43 8 p. (Lecture Notes in Computer Science; vol. 10216)(Theoretical Computer Science and General Issues; vol. 10216).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. VLSI layout and packaging of butterfly networks

    Yeh, CH., Parhami, B., Varvarigos, EA. & Lee, H., 2000, SPAA 2000. New York: Association for Computing Machinery (ACM), p. 196-205 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  52. Variability and reliability analyses in SRAM decoder

    Seyab, MSK. & Hamdioui, S., 2013, 4th Workshop on design for reliability. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. Variable length decoder implemented on a TriMedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 605-610 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. Variation tolerant on-chip degradation sensors for dynamic reliability management systems

    Wang, Y., Enachescu, M., Cotofana, SD. & Fang, L., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  55. Vector ISA extension for sparse matrix-vector multiplication

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 1999, Euro-Par '99 Parallel Processing: proceedings (Lecture notes in computer science 1685). P Amestoy (ed.). Berlin: Springer, p. 708-715 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Vector Processor Customization for FFT

    Spinean, B., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Conference on Embedded Computer Systems: Architecture Modeling and Simulation. Carro, L. & Pimentel, A. (eds.). Piscataway: IEEE Society, p. 110-117 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Vectorized AES core for high-throughput secure environments

    Pericas, M., Chaves Fernandes, R., Gaydadjiev, GN., Vassiliadis, S. & Valero, M., 2008, In : Lecture Notes in Computer Science. 5336, p. 83-94 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  58. Vectorized aes core for high-throughput secure environments

    Pericas, M., Chaves, PC., Gaydadjiev, GN. & Vassiliadis, S., 2007, The future of computing. Gaydadjiev, G Bertels, K, C. S. & Genderen van, A Hamdioui, S, J. B. (eds.). Delft: Computer Engineering TUDelft, p. 91-100 143 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  59. Versatility of extended subwords and the matrix register file

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2008, In : ACM Transactions on Architecture and Code Optimization. 5, 1, p. 1-29 29 p.

    Research output: Contribution to journalArticleScientificpeer-review

  60. Virtual execution platforms for mixed-time-criticality systems: The CompSOC architecture and design flow

    Goossens, KGW., Pereira de Azevedo Filho, AP., Chandrasekar, K., Mirzoyan, D., Molnos, AM., Beyranvand Nejad, A. & Nelson, AT., 2013, In : SIGBED Review. 10, 3, p. 23-34 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  61. Vision-based hand gesture recognition for human computer interaction: a review

    Hassanpour, R., Wong, S. & Shahbahrami, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 125-132 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. Visual data rectangular memory

    Kuzmanov, GK., Gaydadjiev, GN. & Vassiliadis, S., 2004, Euro-Par 2004 Parallel processing. Danelutto, M., Vanneschi, M. & Laforenza, D. (eds.). Berlin: Springer, p. 760-767 8 p. (Lecture Notes in Computer Science; vol. 3149).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS

    Van Staveren, J., Garcia Almudever, C., Scappucci, G., Veldhorst, M., Babaie, M., Charbon, E. & Sebastiano, F., 1 Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers (IEEE), p. 37-40 4 p. 8902861

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. Wave field synthesis for 3D audio: architectural prospectives

    Theodoropoulos, D., Ciobanu, CB. & Kuzmanov, GK., 2009, 2009 ACM international conference on computing frontiers & workshops. n.s. (ed.). New York: Association for Computing Machinery (ACM), p. 127-136 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Weighted embedded zero tree for scalable video compression

    Choupani, R., Wong, S. & Tolun, MR., 2008, Intl. Conf. on Image Processing, Computer Vission and Pattern Recognition. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Weighted embedded zero tree for scalable vidoe compression

    Choupani, R., Wong, S. & Tolun, MR., 2008, Proceedings of the 2008 international conference on image processing, computer vision, & pattern recognition. Arabnia, HR. (ed.). USA: CSREA Press, p. 681-684 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Why is CMOS scaling coming to an END?

    Haron, NZB. & Hamdioui, S., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 98-103 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Wireless SDR solutions: The challenge and promise of next generation handsets

    Glossner, CJ., Hokenek, E. & Moudgill, M., 2002, CDC 2002 Communications Design Conference Proceedings. CMP Media LLC, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  69. Worst-case bit line coupling backgrounds for open defects in SRAM cells

    Irobi, IS. & Al-Ars, Z., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 25-30 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnects at test access mechanism

    Amory, A., Goossens, KGW., Marinissen, E., Lubaszewski, M. & Moraes, F., 2007, In : IET Computers and Digital Techniques. 1, 3, p. 197-206 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  71. Wrapper design for the reuse of networks-on-chip as test access mechanism

    Amory, A., Goossens, KGW. & Marinissen, E., 2006, Proc. European Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 213-218 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. Y'UV-to-R'G'B' color space conversion on FPGA-augmented TriMedia-32 processor

    Sima, M., Vassiliadis, S., van Eijndhoven, JTJ. & Cotofana, SD., 2002, Proceeding ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 465-471 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  73. Yield Improvement for 3D wafer-to-wafer stacked ICs using wafer matching

    Taouil, M., Hamdioui, S. & Marinissen, EJ., 2015, In : ACM Transactions on Design Automation of Electronic Systems. 20, 2, p. 1-23 23 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. Yield and cost analysis or 3D stacked ICs

    Taouil, M., 2014, 215 p.

    Research output: ThesisDissertation (TU Delft)

  75. Yield improvement and test cost optimization for 3D stacked ICs

    Hamdioui, S. & Taouil, M., 2011, 20th IEEE Asian Test Symposium 2011. Chatterjee, A., Patra, A., Kundu, S. & Ravi, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 480-485 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Yield improvement for 3D wafer-to-wafer stacked memories

    Taouil, M. & Hamdioui, S., 2012, In : Journal of Electronic Testing: theory and applications. 28, 4, p. 523-534 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  77. You can catch more bugs with transaction level honey

    Abramovici, MM., Goossens, KGW., Greenbaum, J., Stollon, N. & Donlin, A., 2008, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 121-124 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits

    Safiruddin, S., Lefter, M., Borodin, DV., Voicu, GR. & Cotofana, SD., 2012, ACM International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. eQASM: An executable quantum instruction set architecture

    Fu, X., Riesebos, L., Rol, M. A., Van Straten, J., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., Newsum, V., Loh, K. K. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., Dicarlo, L. & Bertels, K., 2019, Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. Louri, A. & Venkataramani, G. P. (eds.). Piscataway, NJ: IEEE, p. 224-237 14 p. 8675197

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. hArtes: Holistic Approach to Reconfigurable Real-Time Embedded Systems

    Kuzmanov, GK., Sima, VM., Bertels, KLM., Coutinho, G., Luk, W., Marchiori, G., Tripiccione, R. & Ferrandi, F., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hübner, M. (eds.). Berlin - Heidelberg: Springer, p. 91-116 290 p.

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  81. pi-VEX: a reconfigurable and extensible softcore VLIW processor

    Wong, S., As van, T. & Brown, G., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. rSesame - a generic system-level runtime simulation framework for reconfigurable architectures

    Sigdel, K., Thompson, M., Galuzzi, C., Pimentel, AD. & Bertels, K., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 460-464 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. tQUAD-memory bandwith usage analysis

    Ostadzadeh, SA., Corina, M., Galuzzi, C. & Bertels, KLM., 2010, 39th intl. conf. on parallel processing workshops. s.n. (ed.). Piscataway: IEEE Society, p. 217-226 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. using VLIW softcore processors for image processing applications

    Hoozemans, JJ., Wong, S. & Al-Ars, Z., 2015, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV. Soudris, D. & Carro, L. (eds.). Piscataway: IEEE Society, p. 315-318 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. ¿MOS enhanced differential current-switch threshold logic gates

    Li, KC., Padure, MD. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 530-535 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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