201 - 300 out of 1,585Page size: 100
  1. Adaption to dynamic resource availability in ad hoc grids through a learning mechanism

    Pourebrahimi, B. & Bertels, KLM., 2008, 2008 IEEE 11th Intl. Conf. on Computational Science and Engineering. s.n. (ed.). s.l.: s.n., p. 171-178 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Adaptive ILP Control to increase Fault Tolerance for VLIW Processors

    Sartor, A. L., Wong, S. & Beck, A. C. S., Jul 2016, Application-specific Systems, Architectures and Processors (ASAP), 2016 IEEE 27th International Conference on. London, UK: IEEE, p. 9-16 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Adaptive agent-based resource management for GRID

    Abdullah, MT., Bertels, KLM. & Vassiliadis, S., 2006, 12th Annual conference of the advanced school for computing and imaging. Lelieveldt, B. P. F., Haverkort, B., de Laat, C. T. A. M. & Heijnsdijk, J. W. J. (eds.). Delft: ASCI, p. 420-428 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Adaptive clock scheduling for pipelined structures

    Kuiper, B. & Cotofana, SD., 2009, 2009 IEEE/ACM international symposium on nanoscale architectures. s.n. (ed.). Piscataway: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Adaptive fault-tolerant architecture for unreliable technologies with heterogenous variability

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, In : IEEE Transactions on Nanotechnology. 11, 4, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Adaptive gaussian mixture for skin color segmentation

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2008, Proceeding of World Academy of Science, Engineering and Technology. s.n. (ed.). s.l.: WASET org., p. 1-6 6 p. (World Academy of Science, Engineering and Technology. Proceedings; vol. 31).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Adaptive, low-power architectures for embedded multimedia systems: with focus on H.264/AVC video codec

    Nadeem, M., 2014, 136 p.

    Research output: ThesisDissertation (TU Delft)

  8. Addition related arithmetic operations via controlled transport of charge

    Cotofana, SD., Lageweg, CR. & Vassiliadis, S., 2005, In : IEEE Transactions on Computers. 54, 3, p. 243-256 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Address and data scrambling: causes and impact on memory tests

    van de Goor, AJ. & Schanstra, I., 2002, International workshop on Electronic design, test, and applications. Renovell, M. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 128-137 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Addressing GPU on-chip shared memory bank conflicts using elastic pipeline

    Gou, C. & Gaydadjiev, GN., 2013, In : International Journal of Parallel Programming. 41, 3, p. 400-429 30 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Advanced NEMS-based power management for 3D stacked integrated circuits

    Enachescu, M., Voicu, GR. & Cotofana, SD., 2010, 2010 Intl. conf. on energy aware computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Advanced Profiling of Applications for Heterogeneous Multi-Core Platforms

    Bertels, KLM., Meeuws, RJ. & Ostadzadeh, SA., 2011, Proceedings of 2011 International Conference on Engineering of Reconfigurable Systems & Algorithms. Plaks, TP. (ed.). CSREA Press, p. 171-183 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Aelite: a flit-synchronous network on chip with composable and predictable services

    Hansson, A., Subburaman, M. & Goossens, KGW., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 250-255 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Agent based local ad hoc grids

    Abdullah, MT. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 284-287 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Agent based social simulation in markets

    Bertels, KLM. & Boman, M., 1999, WAEC'99: proceedings. Yiming Ye & Jiming Liu (eds.). S.l.: s.n., p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  16. Agent toolkits for ad hoc grids

    Abdullah, MT. & Bertels, K., 2009, Proceedings of the 1st international workshop on distributed computing in ambient environments. Brimkmann, A., Eikerling, H-J. & Zaheer Aziz, M. (eds.). s.l.: s.n., p. 49-58 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Agent-based social simulation in markets

    Bertels, KLM. & Boman, M., 2001, In : Electronic Commerce Research. 1, 1-2, p. 149-158 10 p.

    Research output: Contribution to journalArticleScientific

  18. Aging assessment and reliability aware omputing platforms

    Wang, Y., 2013, 126 p.

    Research output: ThesisDissertation (TU Delft)

  19. Aging mitigation in memory arrays using self-controlled bit-flipping technique

    Gebregiorgis, A., Ebrahimi, M., Kiamehr, S., Oboril, F., Hamdioui, S. & Tahoori, MB., 2015, Proceedings - 20th Asia and South Pacific Design Automation Conference. Uchiyama, K. (ed.). Piscataway, NJ, USA: IEEE Society, p. 231-236 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Algorithm development for scalable processor systems based on transport triggered architectures

    Corporaal, H., 1999, Proceedings. AB Smolders & MP Haarlem, V. (eds.). Dwingeloo: ASTRON, p. 225-234 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  21. Algorithmic Skeletons for Stream Programming in Embedded Heterogeneous Parallel Image Processing

    Caarls, W., Jonker, PP. & Corporaal, H., 2006, Proc. 20th IEEE International Parallel & Distributed Processing Symposium. s.n. (ed.). Rhodos: s.l., p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Algorithms for the automatic extension of an instruction-set

    Galuzzi, C., Theodoropoulos, D., Meeuws, RJ. & Bertels, K., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 548-553 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Alternative architectures toward reliable memristive crossbar memories

    Vourkas, I., Stathis, D., Sirakoulis, G. C. & Hamdioui, S., 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 206-217 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. Alternatives in FPGA-based SAD implementations

    Wong, JSSM., Stougie, B. & Cotofana, SD., 2002, 2002 IEEE international conference on field-programmable technology (FPT). Piscataway: IEEE Society, p. 449-452 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. An 8-point IDCT computing resource implemented on a trimedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., van Eijndhoven, JTJ. & Vassiliadis, S., 2001, Proceedings. F Karelse (ed.). Utrecht: STW Technology Foundation, p. 211-218 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM

    van Dam, L., Peltenburg, J., Al-Ars, Z. & Hofstee, H. P., 2019, CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019. New York, NY: Association for Computing Machinery (ACM), p. 5:1--5:10 10 p. 5

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1},

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 8, p. 1500-1503 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, In : SIGARCH Computer Architecture News. 44, 4, p. 38-43 6 p.

    Research output: Contribution to journalArticleScientific

  29. An Efficient GPU-based de Bruijn Graph Construction Algorithm for Micro-Assembly

    Ren, S., Ahmed, N., Bertels, K. & Al-Ars, Z., 2018, Proceedings - 2018 IEEE 18th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2018). Bourbakis, N. G. & Kavraki, D. (eds.). Piscataway, NJ, USA: IEEE, p. 67-72 6 p. 8567459

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. An Efficient Hardware Design for Intra-prediction in H.264/AVC Decoder

    Nadeem, M., Wong, JSSM. & Kuzmanov, GK., 2011, Saudi International Electronics, Communications and Photonics Conference 2011 (SIECPC). s.n. (ed.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Lee, J., Al-Ars, Z. & Hofstee, P., 2020, In : Journal of Signal Processing Systems. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  32. An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems

    Beyranvand Nejad, A., Escudero Martinez, M. & Goossens, KGW., 2011, Design, Automation and Test in Europe Conference and Exhibition (DATE 2011). Al-Hashimi, BM. (ed.). Leuven, Belgium: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

    Houtgast, E., Sima, VM., Bertels, K. & Al-Ars, Z., 28 Dec 2015, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV. Soudris, D. & Carro, L. (eds.). Piscataway, NJ, USA: IEEE Society, p. 221-227 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. An Image Processing VLIW Architecture for Real-Time Depth Detection

    Iorga, D., Nane, R., Lu, Y., van Dalen, E. & Bertels, K., 2016, Proceedings - 28th IEEE International Symposium on Computer Architecture and High Performance Computing: SBAC-PAD 2016. Baldassin, A. (ed.). Piscataway: IEEE, p. 158-165 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2018, Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, p. 999-1000 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. An Instruction to Accelerate Software Caches

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2011, Proceedings of the 2011 Conference on Architecture of Computing Systems. Berekovic, M., Fornaciari, W., Brinkschulte, U. & Silvano, C. (eds.). Heidelberg: Springer, p. 158-170 13 p. (Lecture Notes in Computer Science; vol. LNCS 6566).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. An OCM based shared memory controller for virtex 4

    Breijer, B., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 692-696 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. An Overview of Hardware-based Acceleration of Biological Sequence Alignment

    Hasan, L. & Al-Ars, Z., 2011, Computational Biology and Applied Bioinformatics. Lopes, HS. & Cruz, LM. (eds.). Reijka, Croatia: Intech, p. 187-202 442 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  39. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. An analysis of limited wavelength translation in regular all-optical WDM networks

    Sharma, A. & Varvarigos, EA., 2001, In : Journal of Lightwave Technology. 18, 12, p. 1606-1619 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  42. An analysis of oblivious and adaptive routing in optical networks with wavelength translation

    Lang, JP., Sharma, A. & Varvarigos, EA., 2001, In : IEEE - ACM Transactions on Networking. 9, 4, p. 503-517 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  43. An analysis of rule-set databases in packet classification

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 110-115 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability

    Yang, B., Grandhi, S., Spagnol, C., Popovici, E. & Cotofana, S., 2016, Proceedings - 27th Irish Signals and Systems Conference. Curran, K. (ed.). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. An approach for optimal bandwidth allocation in packet processing systems

    Ahmadi, M. & Wong, S., 2008, CNSR 2008 conference. s.n. (ed.). s.l.: s.n., p. 208-214 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. An artificial stock market

    Neuberg, L. & Bertels, KLM., 2002, Applied Informatics International symposium on artifcial intelligence and applications: Proceedings of the IASTED International Conference. Hamza, MH. (ed.). Anaheim: ACTA Press, p. 308-314 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  47. An attitude determination system suitable for a spacecraft

    Amini, R., Gill, EKA. & Gaydadjiev, GN., 2010, IPC No. aanvrager: TU Delft, Patent No. NL48.293-VB, Priority date 1 Jan 1800

    Research output: Patent

  48. An economic framework for resource allocation in ad-hoc grids

    Pourebrahimi, B., 2009, 144 p.

    Research output: ThesisDissertation (TU Delft)

  49. An efective routing algorithm to avoid unnecessary link abandon in 2D mesh NoCs

    Chen, C. & Cotofana, SD., 2013, 16th Euromicro Conference on Digital System Design. s.n. (ed.). Piscataway: IEEE Society, p. 311-318 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. An effective new CRT based reverse converter for a novel moduli set { 2^(2n+1)-1, 2^(2n+1), 2^(2n)-1 }

    Bankas, EK., Gbolagade, KA. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA , USA: IEEE, p. 142-146 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. An efficient FPGA design of reverse converter for the moduli set {2n+2, 2n+1, 2n}

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2010, Advanced computer architecture and compilation for high-performance and embedded systems. s.n. (ed.). s.l.: s.n., p. 117-120 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  52. An efficient RNS to binary converter using the moduli set {2n+1, 2n, 2n-1}

    Gbolagade, KA. & Cotofana, SD., 2008, Conference on Design of Circuits and Integrated Systems. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. An efficient algorithm for free resources management on the FPGA

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1095-1098 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. An efficient and high performance linear recursive variable expansion implementation of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2009, 31st annual international conference of the IEEE engineering in medicine and biology society. s.n. (ed.). Piscataway: IEEE Society, p. 3845-3848 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. An efficient realization of forward integer transform in H.264/AVC intra-frame encoder

    Nadeem, M., Wong, S. & Kuzmanov, GK., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 71-78 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. An efficient software cache for H.264 motion compensation

    Pereira de Azevedo Filho, AP. & Juurlink, B., 2009, 2009 international symposium on system-on-chip proceedings. s.n. (ed.). Piscataway: IEEE Society, p. 147-150 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. An empirical comparison of ANSI-C to VHDL compilers: SPARK, ROCCC and DWARV

    Virginia, A., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 388-394 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. An energy effective SIMD accelerator for visual pattern matching

    Bira, C., Gugu, L., Hobincu, R., Codreanu, V., Petrica, L. & Cotofana, SD., 2013, 4th International symposium on highly efficient accelerators and reconfigurable technologies. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. An energy-aware architectural exploration tool for ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2001, S.l.: s.n. 24 p.

    Research output: Book/ReportReportProfessional

  60. An energy-aware architectural exploration tool for ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 327-337 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. An evaluation of FPGA-based IDS pattern matching techniques

    Sourdis, I., Pnevmatikatos, DN. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 449-453 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. An experience with Chalcogenide memristors, and implications on memory and computer applications

    Escudero-López, M., Amat, E., Rubio, A. & Pouyan, P., 2017, 2016 Conference on Design of Circuits and Integrated Systems (DCIS). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. An experimental analysis of spot defects in SRAMs: realistic fault models and test

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Proceedings of the ninth Asian test symposium. DC Young (ed.). Piscataway: IEEE Society, p. 131-138 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. An experimental microarchitecture for a superconducting qantum processor

    Fu, X., Rol, M. A., Bultink, C. C., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., DiCarlo, L. & Bertels, K., 14 Oct 2017, MICRO 2017 - 50th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings. IEEE, Vol. Part F131207. p. 813-825 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. An implementation of the MPEG-4 ACQ function

    Kuzmanov, G., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRICS 2001: proceedings. Utrecht: STW Technology Foundation, p. 466-469 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set

    Gbolagade, KA., Chaves Fernandes, R., Sousa, L. & Cotofana, SD., 2010, IEEE intl. symposium on circuits and systems. Piscataway: IEEE Society, p. 2103-2106 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. An improved algorithm for slot selection in the Æthereal Network-on-Chip

    Stefan, RA. & Goossens, KGW., 2011, Proceedings of the Fifth ACM Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC). Flich, J., Bertozzi, D., Skei, T. & Ludovici, D. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 7-10 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. An improved system approach towards future cochlear implants

    Lawand, NS., Ngamkham, W., Nazarian, G., French, PJ., Serdijn, WA., Gaydadjiev, GN., Briaire, JJ. & Frijns, JHM., 2013, Proceedings - 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society in conjuction with the 52nd Annual Conference of Japanese Society for Medical and Biological Engineering (JSMBE). Wheeler, B. (ed.). Piscataway, NJ, USA: IEEE Society, p. 5163-5166 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. An industrial evaluation of DRAM tests

    van de Goor, AJ., 2004, In : IEEE Design & Test of Computers. 21, 5, p. 430-440 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  70. An input weights aware synthesis tool for threshold logic networks

    Zhang, L. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 578-583 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  71. An investigation into multicasting

    Manolov, N., Gamil, A. & Wong, JSSM., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 523-528 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. An investigation on FPGA based SAD hardware implementations

    Wong, JSSM., Stougie, B. & Cotofana, SD., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 567-573 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  73. An o(n) residue number system to mixed radix conversion technique

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international symposium on circuits and systems. Piscataway: IEEE Society, p. 521-525 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

    Hansson, A. & Goossens, KGW., 2009, 7th IEEE/ACM intl. conf. on hardware/software codesign and system synthesis. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 99-108 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. An optimization framework for retargetable compilers

    Panainte, E., Athanasiu, I. & Cotofana, SD., 2001, CSCS-13: proceedings. I Dumitrache & C Buiu (eds.). Bucharest: Editura Politehnica, p. 427-432 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Analog television, WiMAX and DVB-H on the same SoC platform

    Iancu, D., Ye, H., Kotlyar, V., Senthilvelan, M., Glossner, CJ., Nacer, G., Iancu, A. & Takala, J., 2006, 2006 International Symposium on System-on-Chip. s.n. (ed.). Piscataway: IEEE Society, p. 28-31 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. Analog-to-digital converter based on single-electron tunneling transistors

    Hu, C., Cotofana, SD., Jiang, J. & Cai, Q., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 11, p. 1209-1213 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  78. Analyses of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, 2008 IEEE International Symposium on Circuits and Systems. s.n. (ed.). s.l., p. 488-491 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Analysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices

    Irobi, IS., 2011, Delft: IS Irobi. 132 p.

    Research output: ThesisDissertation (TU Delft)

  80. Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics

    Veneman, WJ., de Sonneville, J., van der Kolk, KJ., Ordas, A., Al-Ars, Z., Meijer, AH. & Spaink, HP., 2015, In : Immunogenetics. 67, 3, p. 135-147 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. Analysis of a reconfigurable network processor

    Kachris, C. & Vassiliadis, S., 2006, Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 192-192

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. Analysis of a user-space device-driver for the memcpy hardware

    Campos Soares Borrego, F. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 138-143 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Analysis of analog to digital converter based on single-electron tunneling transistors

    Hu, C., Cotofana, SD. & Jiang, J., 2004, Proceedings of 2004 IEEE international symposium on circuits and systems. Los Alamitos: IEEE, p. 693-696 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Analysis of delay mismatching of digital circuits caused by common environmental fluctuations

    Andrade, D., Rubio, A., Calomarde, A. & Cotofana, SD., 2011, Proceedings 2011 IEEE International Symposium on Circuits and Systems. Silva, EAB. & Lande, TS. (eds.). Piscataway, NJ, USA: IEEE Society, p. 2585-2588 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

    Wang, Y., Cotofana, SD. & Fang, L., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2521-2529 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  86. Analysis of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 116-121 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. Analyzing combined impacts of parameter variations and BTI in nano-scale logical gates

    Seyab, MSK. & Hamdioui, S., 2012, 1st Workshop on manufacturable and dependable multicore architectures at nanoscale. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. Analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 189-194 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Analyzing the impact of process variations on DRAM testing using border resistance traces

    Al-Ars, Z. & van de Goor, AJ., 2003, ATS 2003; proceedings of the twelfth Asian test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 24-27 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. Ant colony inspired microeconomic based resource management in ad hoc grids

    Abdullah, MT., Bertels, K. & Onana Alima, L., 2009, In : Lecture Notes in Computer Science. 5529, p. 189-198 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Application of Transient Heat Flux Sensors to Resolve Time-Dependent Convective Heat Transfer from Wall-mounted Cubes

    Meinders, ER., Geuzebroek, MJ., Hanjalic, K. & Ortega, A., 1998, ASME Conference. Nelson, RA., Chopin, T. & Thynell, ST. (eds.). p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  92. Application-specific parallel structures for discrete cosine transform and variable length decoding

    Nikara, J., 2004, Tampere, Finland: Tampere University of Technology. 127 p.

    Research output: ThesisDissertation (external)

  93. Applications of Computation-In-Memory Architectures based on Memristive Devices

    Hamdioui, S., Du Nguyen, H. A., Taouil, M., Sebastian, A., Le Gallo, M., Pande, S., Schaafsma, S., Catthoor, F., Das, S., G. Redondo, F., Karunaratne, G., Rahimi, A. & Benini, L., 2019, Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019: Proceedings. IEEE, p. 486-491 6 p. 8715020

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. Applying dataflow analysis to dimension buffers for guaranteed performance in networks on chip

    Hansson, A., Wiggers, M., Moonen, A., Goossens, KGW. & Bekooij, M., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 211-212 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Approximating infinite dynamic behavior for DRAM cell defects

    Al-Ars, Z. & van de Goor, AJ., 2002, 20th VLSI Test symposium Proceedings. Piscataway, NJ, USA: IEEE Society, p. 401-407 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. Approximating the optimal replacement algorithm

    Juurlink, BHH., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 313-319 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Arbitrating instructions in an ¿¿-coded CCM

    Kuzmanov, GK. & Vassiliadis, S., 2003, Field-programmable logic and applications; 13th international conference, FPL 2003. Cheung, PYK., Constantinides, GA. & de Sousa, JT. (eds.). Berlin: Springer, p. 81-90 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. Architectural Exploration of the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., Kanstein, A. & Gaydadjiev, GN., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 1-13 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  99. Architectural Support for Multithreading on Reconfigurable Hardware

    Zaykov, P. & Kuzmanov, GK., 2011, International Symposium on Applied Reconfigurable Computing. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R. & El-Ghazawi, T. (eds.). Heidelberg: Springer, p. 363-374 12 p. (Lecture Notes in Computer Science; vol. 6578).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. Architectural support for 3D graphics in the complex streamed instruction set

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2002, In : International Journal of Parallel and Distributed Systems & Networks. 5, 4, p. 185-193 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

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