301 - 400 out of 1,585Page size: 100
  1. Architectural support for 3D graphics in the complex streamed instruction set

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2002, Parallel and distributed computing and systems; Proceedings of the 14th IASTED International conference. Akl, SG. & Gonzalez, T. (eds.). Anaheim: ACTA Press, p. 536-542 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Architecture and design flow for a debug event distribution interconnect

    Pereira de Azevedo Filho, AP., Vermeulen, B. & Goossens, KGW., 2012, 30th IEEE International conference on computer design. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Architecture design principles for the integration of synchronization interfaces into network-on-chip switches

    Ludovici, D., Strano, A. & Bertozzi, D., 2009, Second International workshop on network on chip architectures. s.n. (ed.). New York, NY, USA: Association for Computing Machinery (ACM), p. 31-36 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Architecture enhancements for the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., de Sutter, B. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 66-81 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Architecture of high speed switches and internet routers

    Mhamdi, LL. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 62-65 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Area constraint propagation in high level synthesis

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on field-programmable technology. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Area efficient, High speed parallel counter circuits using charge recycling threshold logic

    Celinski, P., Abbott, D. & Cotofana, SD., 2003, ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems. Piscataway: IEEE Society, p. 233-236 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Arithmetic soft-core accelerators

    Calderon, H., 2007, Delft: H. calderon. 155 p.

    Research output: ThesisDissertation (TU Delft)

  9. Array based structure loop transformations for cache miss reduction

    Stanca, VM., Corporaal, H., Cotofana, SD. & Vassiliadis, S., 2000, Proceedings. MH Hamza (ed.). Annaheim: iASTED, p. 278-284 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. Array processor communication architecture with broadcast instructions

    Pechanek, GG., Vassiliadis, S., Glossner, CJ. & Larsen, LD., 2000, Priority date 26 Jul 2000

    Research output: Patent

  11. ArrowSAM: In-Memory Genomics Data Processing Using Apache Arrow

    Ahmad, T., Ahmed, N., Peltenburg, J. & Al-Ars, Z., 2020, 2020 3rd International Conference on Computer Applications & Information Security (ICCAIS): Proceedings. IEEE, p. 1-6 6 p. 9096725

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

    Ludovici, D., Gilabert, F., Medardoni, S., Gomez, C., Gomez, ME., Lopez, P., Gaydadjiev, GN. & Bertozzi, D., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 562-565 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Asynchronous Charge Sharing Power Consistent Montgomery Multiplier

    Chen, J., Tisserand, A., Popovici, E. & Cotofana, SD., 2015, Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems. Jones, IW. & Sparso, J. (eds.). Piscataway: IEEE Society, p. 132-138 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Atomistic-level hysteresis-aware graphene structures electron transport model

    Wang, H., Cucu Laurenciu, N., Jiang, Y. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. p. 1-5 5 p. 8702106

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Auction protocols for resource allocations in ad-hoc grids

    Pourebrahimi, B. & Bertels, KLM., 2008, In : Lecture Notes in Computer Science. LNCS5168, p. 520-533 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

    Papameletis, C., Keller, B., Chickermane, V., Marinissen, EJ. & Hamdioui, S., 2013, 18th IEEE European Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Automated HDL generation: comparative evaluation

    Yankova, YD., Bertels, K., Vassiliadis, S., Meeuws, RJ. & Virginia, A., 2007, 2007 IEEE intl. Symposium on Circuits and Systems. Piscataway: IEEE Society, p. 2750-2753 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. Automated design of an ASIP for image processing applications

    Schot, HJM. & Corporaal, H., 2000, In: A Bode, ...[et al.] (eds): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 1105-1109 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. Automated digital circuits design based on single-grain si TFTs fabricated through u-Czochralski (grain filter) process

    Fang, W., van Genderen, AJ., Ishihara, R., Vikas, R., Karaki, N., Hiroshima, Y., Inoue, S., Shimoda, T., Metselaar, JW. & Beenakker, CIM., 2006, The 13th intl. workshop on Active-Matrix flatpanel displays and devices. s.n. (ed.). Japan: Japan Society of Applied Physics, p. 47-50 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Automated hybrid interconnect design for FPGA accelerators using data communication profiling

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, K., 2014, Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops. Parashar, M. (ed.). Los Alamitos, CA, USA: IEEE, p. 151-160 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Automatic SIMD parallelization of embedded applications based on pattern recognition

    Manniesing, R., Karkowski, I. & Corporaal, H., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 349-356 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  22. Automatic VHDL model generation of parameterized FIR filters

    Walters III, EG., Glossner, CJ. & Schulte, MJ., 2004, Domain-specific processors. Bhattacharyya, SS., Deprettere, EF. & Teich, J. (eds.). New York: Marcel Dekker, p. 1-18 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  23. Automatic VHDL model generation of parameterized FIR filters

    Walters III, EG., Glossner, CJ. & Schulte, MJ., 2002, Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation-Proceedings. Leiden: SAMOS Initiative, p. 1-14 14 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  24. Automatic analyses of memory faulty behaviour in defective memories

    Al-Ars, Z. & Hamdioui, S., 2007, Design & Technology of Integrated Systems 2007. Hamdiuoi, S., O. A. (ed.). Piscataway: IEEE Society, p. 41-46 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Automatic hardware generation for reconfigurable architectures

    Nane, R., 2014, 179 p.

    Research output: ThesisDissertation (TU Delft)

  26. Automatic hardware generation for the Molen reconfigurable architecture: a G721 case study

    Theodoropoulos, D., Yankova, YD., Kuzmanov, GK. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 380-387 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Automatic instruction-set extensionswith the linear complexity spiral search

    Galuzzi, C., Theodoropoulos, D., Meeuws, RJ. & Bertels, K., 2008, 2008 international conference on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 31-36 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Automatic selection of application-specific instruction-set extensions

    Galuzzi, C., Panainte, E., Yankova, YD., Bertels, K. & Vassiliadis, S., 2006, Intl. Conf. on Hardware/Software Codesign and Systems Synthesis. s.n. (ed.). Piscataway: IEEE Society, p. 160-165 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Automatically fused instructions algorithm for the customization of the instruction-set of a reconfigurable architecture

    Galuzzi, C., 2009, Delft: s.n.. 170 p.

    Research output: ThesisDissertation (TU Delft)

  30. Automating defects simulation and fault modeling for SRAMs

    Di Carlo, S., Prinetto, P., Scionti, A. & Al-Ars, Z., 2008, IEEE Intl. High Level Design Validation and Test workshop 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Autonomic computing systems: issues and challenges

    Nami, MR., Bertels, KLM. & Vassiliadis, S., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 538-543 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Avoiding conversion and rearrangement overhead in SIMD architectures

    Shahbahrami, A., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)

  33. Avoiding conversion and rearrangements overhead in SIMD architectures

    Shahbahrami, A., Juurlink, B., Borodin, D. & Vassiliadis, S., 2006, In : International Journal of Parallel Programming. 34, 3, p. 237-260 24 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. Avoiding data conversions in embedded media processors

    Juurlink, BHH., Shahbahrami, A. & Vassiliadis, S., 2005, Proceedings of the 20th ACM symposium on applied computing. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 901-902 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. BBCS based sparse matrix-vector multiplication: initial evaluation

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, Proceedings. M Deville & R Owens (eds.). New Brunswick: IMACS, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  36. BIST enhancement for detecting bit/byte write enable faults in SOC SCRAMs

    Hamdioui, S., Al-Ars, Z., Jimenez, J. & Calero, J., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. BRAM-LUT tradeoff on a polymorphic DES design

    Chaves Fernandes, R., Donchev, B., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 55-65 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  38. BTI Impacts on logical gates in nano-scale CMOS technology

    Seyab, MSK., Hamdioui, S., Kukner, H., Catthoor, F. & Raghavan, P., 2012, 15th IEEE Symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. BTI analysis of SRAM write driver

    Agbo, IO., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 2015, Proceedings of the 10th International Design and Test Symposium, IDT 2015. Kurdahi, F., Mir, S. & Yu, MO. (eds.). Piscataway: IEEE Society, p. 100-105 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Badwidth analysis of functional interconnects used as test access mechanism

    van den Berg, A., Ren, P., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2010, In : Journal of Electronic Testing: theory and applications. 26, 4, p. 453-464 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector

    Kritchallo, V., Braithwaite, B., Vermij, E., Bertels, K. & Al-Ars, Z., 2016, Architecture of Computing Systems- ARCS 2016: Proceedings of the 29th International Conference on Architecture of Computing Systems. Hannig, F., Cardoso, J. M. P., Pionteck, T., Fey, D., Schröder-Preikschat, W. & Teich, J. (eds.). Cham: Springer, p. 251-262 12 p. (Lecture Notes in Computer Science; vol. 9367).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Bandwidth analyses for reusing functional interconnect as test access mechanism

    van den Berg, A., Ren, R., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2008, 13th European test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 21-26 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Basic building blocks for effective single electron tunneling technology based computation

    Meenderinck, CH. & Cotofana, SD., 2006, Proceedings 2006 International Semiconductor conference. s.n. (ed.). Piscataway: IEEE Society, p. 57-60 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Beamforming in sparse, random, 3D array antennas with fluctuating element locations

    Bentum, M. J., Lager, I. E., Bosma, S., Bruinsma, W. P. & Hes, R., 2015, 2015 9th European Conference on Antennas and Propagation, EuCAP 2015. Piscataway, NJ: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Benchmarking and profiling the RSVP protocol

    Zhao, Y. & Wong, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 470-474 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  46. Better than worst-case design for streaming applications under process variation

    Mirzoyan, D., 2013, Delft: D. Mirzoyan. 106 p.

    Research output: ThesisDissertation (TU Delft)

  47. Bias temperature instability analysis in SRAM decoder

    Seyab, MSK., Hamdioui, S., Kukner, H., Raghavan, P. & Catthoor, F., 2013, Proceedings 18th IEEE European Test Symposium. Girard, P. & Peng, Z. (eds.). Los Alamitos, CA, USA: IEEE Society, p. 1-1 1 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Bias temperature instability analysis of FinFET based SRAM cells

    Seyab, MSK., Agbo, IO., Hamdioui, S., Kukner, H., Kaczer, B., Raghavan, P. & Catthoor, F., 2014, Proceedings of the 2014 International Conference on Design, Automation & Test in Europe. Nebel, W. & Fettweis, G. (eds.). Leuven, Belgium: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Bias temperature instability analysis, monitoring and mitigation for nano-scaled circuits

    Seyab, MSK., 2013, 133 p.

    Research output: ThesisDissertation (TU Delft)

  50. Binary addition based on single electron tunneling devices

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2004, IEEE-NANO 2004 Proceedings. Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Binary multiplication based on Single Electron Tunneling

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 152-166 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Bioinformatics specific cell BE ISA extensions

    Isaza, S. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 52-55 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. Bit line coupling memory tests for single cell fails in SRAMs

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2010, 28th IEEE VLSI test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. Bit-Flip Aware Control-Flow Error Detection

    Nazarian, G., Rodrigues, DG., Moreira, A., Carro, L. & Gaydadjiev, GN., 2015, Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2015. Daneshtalab, M., Aldinucci, M., Leppanen, V., Lilius, J. & Brorsson, M. (eds.). Piscataway: IEEE Society, p. 215-221 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. Bitstream compression techniques for virtex 4 FPGAS

    Stefan, RA. & Cotofana, SD., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 323-328 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Block based compression storage expected performance

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, HPC 2000: proceeding. NJ Dimopoulos & KF Li (eds.). S.l.: Kluwer Academic Publishers, p. 389-406 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Bluetooth protocol profiling on the Xilinx Virtex II pro

    Campos Soares Borrego, F. & Wong, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 495-501 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  58. Boolean Logic Gate Exploration for Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2016, Proceedings - 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016. Danvers, MA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  60. Branch instruction processor and method

    Blaner, B., Jeremiah, TL., Vassiliadis, S. & Williams, PG., 2000, Priority date 19 May 1999

    Research output: Patent

  61. Brownian Circuits: Designs

    Lee, J., Peper, F., Cotofana, S., Naruse, M., Ohtsu, M., Kawazoe, T., Takahashi, Y., Shimokawa, T., Kish, L. B. & Kubota, T., 2016, In : International Journal of Unconventional Computing. 12, 5-6, p. 341-362 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  62. Buffer design trade-offs for single electron logic gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2005, Proceedings of 2005 5th IEEE Conference on Nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 433-436 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Buffered crossbar fabrics based on network on chip

    Mhamdi, LL., Goossens, KGW. & Varela Senin, I., 2010, 8th annual communication networks and services research conference. s.n. (ed.). Piscataway: IEEE Society, p. 74-79 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. Building blocks for MPEG stream processing

    Wong, JSSM., van Kester, J., Konstapel, M., Serra, R. & Visser, O., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 556-560 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  65. Building blocks for delay-insensitive circuits using single electron tunneling devices

    Safiruddin, S. & Cotofana, SD., 2007, 2007 7th IEEE international conference on nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 704-708 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Building blocks for electron counting arithmetic

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 222-228 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Building blocks for fluctuation based calculation in single electron tunneling technology

    Safiruddin, S., Cotofana, SD., Peper, F. & Lee, J., 2008, 2008 eighth IEEE conference on nanotechnology. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra

    Sendir, B., Govindaraju, M., Odaira, R. & Hofstee, P., 2018, 2018 IEEE 11th International Conference on Cloud Computing (CLOUD). Bilof, R. (ed.). Piscataway: IEEE, p. 220-228 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. CCproc: a custom VLIW cryptography co-processor for symmetric-key ciphers

    Theodoropoulos, D., Siskos, A. & Pnevmatikatos, DN., 2009, In : Lecture Notes in Computer Science. 5453, p. 318-323 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  70. CHOP: Haplotype-aware path indexing in population graphs

    Mokveld, T., Linthorst, J., Al-Ars, Z., Holstege, H. & Reinders, M., 2020, In : Genome biology. 21, 1, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  71. CIM-SIM: Computation in Memory SIMuIator

    Banagozar, A., Vadivel, K., Stuijk, S., Corporaal, H., Wong, S., Lebdeh, M. A., Yu, J. & Hamdioui, S., 27 May 2019, SCOPES'19: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems. Stuijk, S. (ed.). New York, NY: Association for Computing Machinery (ACM), p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. CIM100x: Computation in-Memory Architecture Based on Resistive Devices

    Hamdioui, S., Taouil, M., Du Nguyen, H. A., Haron, A., Xie, L. & Bertels, K., 2016, Proceedings of CNNA 2016: 15th International Workshop on Cellular Nanoscale and their Applications. Berlin: VDE, p. 95-96 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. CMOS implementation of generalized threshold functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2003, Computatational methods in neural modeling: seventh international work-conference on artificial and natural neural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 65-72 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. CMOS scaling impacts on reliability, what do we understand?

    Seyab, MSK., Haron, NZB. & Hamdioui, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 260-266 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. CONAN - a design exploration framework for reliable nano-electronics architectures

    Cotofana, SD., Schmid, A., Leblebici, Y., Ionescu, A., Soffke, O., Zipf, P., Glesner, M. & Rubio, A., 2005, Proceedings of the 16th IEEE International conference on Application-Specific Systems Architectures and Processors (ASAP). Vassiliadis, S., Dimopoulos, N. & Rajopadhye, S. (eds.). Los Alamitos: IEEE Society, p. 260-267 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. CORDIC scenario for Kalman-based channel estimation

    Sima, M., McGuire, M., Iancu, D. & Glossner, CJ., 2005, Proceedings of the IEEE Pacific Rim conference on communications, computers and signal processing. s.n. (ed.). Piscataway, USA: IEEE Society, p. 165-168 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. CORDIC-augmented sandbridge processor for channel equalization

    Sima, M., Glossner, CJ., Iancu, D., Ye, H., Iancu, A. & Hoane, AJ., 2005, Embedded computer systems: architectures, modeling, and simulation: 5th International workshop, SAMOS 2005. Hämäläinen, TD., Pimentel, AD., Takala, J. & Vassiliadis, S. (eds.). Heidelberg, Germany: Springer, p. 152-162 11 p. (Lecture Notes in Computer Science; vol. 3553).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. CRB analysis of the impact of unknown receiver noise on phased array calibration

    van der Tol, S. & Wijnholds, SJ., 2006, IEEE Workshop on Sensor Array and Multichannel Signal Processing, 2006. IEEE (ed.). Waltham, MA, USA: IEEE Society, p. 185-189 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Cache partitioning options for compositional multimedia applications

    Molnos, AM., Heijligers, MJM., Cotofana, SD. & van Eijndhoven, JTJ., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 86-90 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  80. Cache replacement policies for IP address lookups

    Guo, R., Delgado-Frias, JG. & Wong, S., 2007, 5th IASTEDintl. conf. on Circuits, Signals, and Systems. Delgado-Frias, J. G. (ed.). Zurich: ACTA Press, p. 70-75 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Calculation of worst-case execution time for multicore processors using deterministic execution

    Mushtaq, H., Al-Ars, Z. & Bertels, K., 2015, Proceedings of the 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS. Reis, R. & Nunes de Lima, R. (eds.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. Can SG-FET replace Fet in sleep mode circuits

    Enachescu, M., Cotofana, SD. & Tsamados, D., 2009, 4th international conference on Nano-Networks. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Capacitive threshold logic: a designer perspective

    Padure, MD., Dan, C., Cotofana, SD., Bodea, M. & Vassiliadis, S., 1999, CAS '99 proceedings. Vol. 1. S.l.: IEEE Society, p. 81-84 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

    Ludovici, D., Gaydadjiev, GN., Bertozzi, D. & Benini, L., 2009, Proceedings of the 2009 Great Lakes symposium on VLSI. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 125-128 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. Casta diva-a design for variability platform

    Cotofana, SD. & Meenderinck, CH., 2008, 2008 Intl. Semiconductor Conference. s.n. (ed.). s.l.: IEEE Society, p. 373-376 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. Centralized matchmaking - An empirical study

    Sigdel, K., Li, S., Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2005, Proceedings of the SAFE & ProRISC 2005. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 438-444 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. Centralized matchmaking for minimal agents

    Bertels, K., Panchanathan, N., Vassiliadis, S. & Ebrahimi, BP., 2004, Proceedings of the 16th IASTED International conference Parallel and Distributed Computing and Systems. Gonzalez, T. (ed.). Anaheim: ACTA Press, p. 608-613 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. Challenges and Solutions in Emerging Memory Testing

    Vatajelu, E. I., Prinetto, P., Taouil, M. & Hamdioui, S., 2019, In : IEEE Transactions on Emerging Topics in Computing. 7, 3, p. 493-506 14 p., 7894207.

    Research output: Contribution to journalArticleScientificpeer-review

  89. Challenges in exascale radio astronomy: Can the SKA ride the technologe wave?

    Vermij, E., Fiorin, L., Jongerius, R., Hagleitner, C. & Bertels, KLM., 2015, In : International Journal of High Performance Computing Applications. 29, 1, p. 37-50 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  90. Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation

    Zandrahimi, M., Al-Ars, Z., Debaud, P. & Castillejo, A., 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Teich, J. (ed.). Piscataway, NJ: IEEE, p. 1018-1019 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip

    Hansson, A., Coenen, M. & Goossens, KGW., 2007, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 149-154 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline

    Mushtaq, H. & Al-Ars, Z., 2015, Proceedings of the International Conference on Bioinformatics and Biomedicine. Huan, J., Miyano, S. & Shehu, A. (eds.). Piscataway: IEEE Society, p. 1471-1477 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. Clustering on the move

    Roos, S., Corporaal, H. & Lamberts, R., 2002, MPCS '02 Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  94. Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs

    Wang, C., Li, X., Zhou, X., Chen, Y. & Bertels, K., 2014, p. 248-248. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  95. CoMPSoC: a template for composable and predictable multi-processor system on chips

    Hansson, A., Goossens, KGW., Bekooij, M. & Huisken, J., 2009, In : ACM Transactions on Design Automation of Electronic Systems. 14, 1, p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  96. CoMik: A predictable and cycle-accurately composable real-time microkernel

    Nelson, AT., Beyranvand Nejad, A., Molnos, AM., Koedam, M. & Goossens, KGW., 2014, Proceedings of the 2014 International Conference on Design, Automation & Test in Europe. Fettweis, G. & Nebel, W. (eds.). Leuven, Belgium: EDAA, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Coarse reconfigurable multimedia unit extension

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. K Klöckner (ed.). Los Alamitos: IEEE, p. 235-242 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. Code deformation and lattice surgery are gauge fixing

    Vuillot, C., Lao, L., Criger, B., García Almudever, C., Bertels, K. & Terhal, B. M., 2019, In : New Journal of Physics. 21, 3, 21 p., 033028.

    Research output: Contribution to journalArticleScientificpeer-review

  99. Code generation and optimization for embedded processors

    Cilio, AGM., 2002, Genova, Italy: ECIG Edizioni Culturali Internazionali Genova. 174 p.

    Research output: ThesisDissertation (TU Delft)

  100. Code positioning for VLIW architectures

    Cilio, AGM. & Corporaal, H., 2001, HPCN Europe 2001: proceedings. G Goos & ... [et Al] (eds.). Berlin: Springer, p. 332-343 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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