401 - 500 out of 1,585Page size: 100
  1. Codeword detection for parallel variable length decoding

    Nikara, J., Vassiliadis, S., Takala, J. & Liuha, P., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  2. Collaboration of reconfigurable processors in grid computing for multimedia kernels

    Ahmadi, M., Shahbahrami, A. & Wong, JSSM., 2010, Grid and Pervasive Computing 2010. s.n. (ed.). Berlijn: Springer, p. 5-14 10 p. (Lecture Notes in Computer Science; vol. 6104/2010).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Collaboration of reconfigurable processors in grid computing: Theory and application

    Ahmadi, M., Shahbahrami, A. & Wong, JSSM., 2011, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 27, 6, p. 850-859 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Color space conversion for MPEG decoding on FPGA-augmented trimedia processor

    Sima, M., Vassiliadis, S., Cotofana, SD. & van Eijndhoven, JTJ., 2003, ASAP 2003; Proceedings 2003, the IEEE international conference on application-specific systems, archtectures and processors. Deprettere, E., Bhattacharyya, S., Cavallaro, J., Darte, A. & Thiele, L. (eds.). Piscataway: IEEE Society, p. 250-259 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Combined multiplication and sum-of-squares units

    Schulte, MJ., Marquette, L., Krithivasan, S., Walters, EG. & Glossner, CJ., 2003, ASAP 2003; Proceedings 2003, the IEEE international conference on application-specific systems, archtectures and processors. Deprettere, E., Bhattacharyya, S., Cavallaro, J., Darte, A. & Thiele, L. (eds.). Piscataway: IEEE Society, p. 204-215 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification

    Augusto da Silva, F., Bagbaba, A. C., Hamdioui, S. & Sauer, C., 2020, Proceedings - 2019 IEEE 28th Asian Test Symposium, ATS 2019. Bilof, R. S. (ed.). Piscataway: IEEE, Vol. 2019-December. p. 129-134 6 p. 8949396. (2019 IEEE 28TH ASIAN TEST SYMPOSIUM (ATS)).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Combining voltage scaling and processor shutdown to reduce energy in embedded multiprocessors

    de Langen, P. & Juurlink, B., 2007, Proceeding of the 13th Annual conference of the ASCI. Veenman CJ Jansen FW, P. GEO. (ed.). Delft: ASCI, p. 195-202 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Communication Driven Mapping of Applications on Multicore Platforms

    Ashraf, I., 28 Apr 2016, 107 p.

    Research output: ThesisDissertation (TU Delft)

  9. Communication Service for hardware tasks executed on dynamic and partial reconfigurable resources

    Narayanan, S., Devaux, L. & Sourdis, I., 2011, 2011 IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC). Tsui, C-Y. & Mir, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 196-199 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Communication-Aware Parallelization Strategies for High Performance Applications

    Ashraf, I., Bertels, K., Khammassi, N. & le Lann, JC., 2015, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015. Mohanty, SP. & Belleville, M. (eds.). Piscataway: IEEE Society, p. 539-444 94 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Communication-aware HW/SW co-design for heterogeneous multicore platforms

    Ashraf, I., Ostadzadeh, SA., Meeuws, RJ. & Bertels, KLM., 2012, 10th International workshop on dynamic analysis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Communication-centric SoC debug using transactions

    Vermeulen, B., Goossens, KGW., van Steeden, R. & Bennebroek, M., 2007, 12th IEEE european Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Compact current and current noise models for single-electron tunneling transistors

    Hu, C., Cotofana, SD. & Jiang, J., 2004, IEEE-NANO 2004 Proceedings. Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Compact delay modeling of latch-based threshold logic gates

    Padure, MD., Cotofana, SD., Dan, C., Vassiliadis, S. & Bodea, M., 2002, CAS 2002 Proceedings, Volume 2. Piscataway, NJ, USA: IEEE Society, p. 317-320 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2018, 2018 IEEE 18th International Conference on BioInformatics and BioEngineering (BIBE). Bourbakis, N. G. & Kavraki, D. (eds.). Piscataway, NJ. USA: IEEE, p. 243-246 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Comparative BTI Analysis for Various Sense Amplifier Designs

    Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P. & Catthoor, F., 2016, Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016. IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Comparative BTI analysis in nano-scale circuits lifetime

    Seyab, MSK., Hamdioui, S. & Catthoor, F., 2012, 4th Workshop on design for reliability. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier

    Agbo, IO., Taouil, M., Hamdioui, S., Cosemans, S., Weckx, P., Raghavan, P. & Catthoor, F., 2015, Proceedings - 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015. Casola, V. (ed.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Comparative analysis of soft and hard on-chip interconnects for FPGAs

    Hur, JY., Goossens, KGW., Mhamdi, L. & Wahlah, MA., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Comparing Neural Network Based Decoders for the Surface Code

    Varsamopoulos, S., Bertels, K. & Almudever, C. G., 1 Feb 2020, In : IEEE Transactions on Computers. 69, 2, p. 300-311 12 p., 8880492.

    Research output: Contribution to journalArticleScientificpeer-review

  21. Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

    Ludovici, D., Strano, A., Bertozzi, D., Benini, L. & Gaydadjiev, GN., 2009, International Symposium on network-on-chip. s.n. (ed.). Piscataway: IEEE Society, p. 244-249 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Comparison between color and texture features for image retrieval

    Shahbahrami, A., Borodin, D. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 361-371 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Comparison of an aetheral network on chip and a traditional interconnect for a multi-processor DVB-T system on chip

    Bartels, C., Huisken, J., Goossens, KGW., Groeneveld, P. & van Meerbergen, J., 2006, Proc. IFIP Intl. Conference on Very Large Sale Integration. s.n. (ed.). Puscataway: IEEE Society, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates

    Kukner, H., Khan, F., Weckx, P., Raghavan, P., Hamdioui, S., Kaczer, B., Catthoor, F., van der Perre, L., Lauwereins, R. & Groeseneken, G., 2014, In : IEEE Transactions on Device and Materials Reliability. 14, 1, p. 182-193 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  25. Comparison of static and dynamic faults in 65nm memory technology

    Hamdioui, S., Al-Ars, Z., Gaydadjiev, GN. & delos Reyes, J., 2006, International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Compatibility study of compile-time optimizations for power and reliability

    Nazarian, G., Strydis, C. & Gaydadjiev, GN., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 809-813 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Compiler and openMP framework to allow dynamics hardware allocation on reconfigurable platforms

    Sima, VM. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 108-111 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Compiler assisted runtime adaption

    Sima, VM., 2012, Delft. 129 p.

    Research output: ThesisDissertation (TU Delft)

  29. Compiler assisted runtime task scheduling on a reconfigurable computer

    Sabeghi, M., Sima, VM. & Bertels, K., 2009, 19th international conference on field programmable logic and applications. s.n. (ed.). Piscataway: IEEE Society, p. 44-50 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Compiler controlled dynamic scheduling of program instructions

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 23 Jun 1999

    Research output: Patent

  31. Compiler-aided methodology for low overhead on-line testing

    Nazarian, G., Seepers, R. M., Strydis, C. & Gaydadjiev, GN., 2013, Proceedings - 2013 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Silven, O. & Jeschke, H. (eds.). Piscataway, NJ, USA: IEEE Society, p. 219-226 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Compiler-controlled dynamic instruction dispatch in pipelined processors

    Batten, D., D'Arcy, PG., Glossner, CJ., Jinturkar, S., Thilo, J., Vassiliadis, S. & Wires, K., 2001, Priority date 10 Jul 2001

    Research output: Patent

  33. Compiler-driven FPGA-area allocation for reconfigurable computing

    Panainte, E., Bertels, K. & Vassiliadis, S., 2006, Design Automation & Test in Europe DATE 06. s.n. (ed.). Piscataway: IEEE Society, p. 369-374 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. Compiling for the molen programming paradigm

    Panainte, E., Bertels, KLM. & Vassiliadis, S., 2003, PA3CT; Program acceleration through application and architecture driven code transformations Symposium Proceedings. s.n. (ed.). s.l.: s.n., p. 41-43 3 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  35. Compiling for the molen programming paradigm

    Panainte, E., Bertels, KLM. & Vassiliadis, S., 2003, Field-programmable logic and applications; 13th international conference, FPL 2003. Cheung, PYK., Constantinides, GA. & de Sousa, JT. (eds.). Berlin: Springer, p. 900-910 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Complementary arranged graphene nanoribbon-based boolean gates

    Jiang, Y., Laurenciu, N. C. & Cotofana, S., 17 Jul 2018, Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Cotofana, S. & Sirakoulis, G. C. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 51-57 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Complex streamed instructions: introduction and initial evaluation

    Vassiliadis, S., Juurlink, BHH. & Hakkennes, EA., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 400-408 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  38. Component-based development in multi agent systems

    Bertels, KLM. & Boman, M., 2002, Net.object days; Offizielle Nachfolge-Veranstaltung der JavaDays, STJA, JIT, DJEK. Ilmenau, Germany: Organisatoren Net.ObjectDays, p. 185-194 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  39. Composable Local Memory Organisation for Streaming Applications on Embedded MPSoCs

    Ambrose, JA., Molnos, AM., Nelson, AT., Cotofana, SD., Goossens, KGW. & Juurlink, BHH., 2011, 8th ACM International Conference on Computing Frontiers. Cascaval, C., Trancoso, P. & Prasanna, V. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Composable and persistent-state application swapping on FPGAs using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 380-385 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Composable and predictable power management

    Nelson, AT., 2014, 193 p.

    Research output: ThesisDissertation (TU Delft)

  42. Composable dynamic voltage and frequency scaling and power management for dataflow applications

    Goossens, KGW., She, D., Milutinovic, A. & Molnos, AM., 2010, 13th euromicro conf. on digital system design. s.n. (ed.). Piscataway: IEEE Society, p. 107-114 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Composable power management with energy and power budgets per application

    Nelson, AT., Molnos, AM. & Goossens, KGW., 2011, Proceedings 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Carro, L. & Pimentel, AD. (eds.). Piscataway, NJ, USA: IEEE Society, p. 396-403 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Composable processor virtualization for embedded systems

    Molnos, AM., Milutinovic, A., She, D. & Goossens, KGW., 2010, 1st workshop on Computer Architecture and operating system co-design. s.n. (ed.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Composable resource sharing based on latency-rate servers

    Akesson, B., Hansson, A. & Goossens, KGW., 2009, 12th Euromicro conference on digital system design architectures, methods and tools. Nunez, A. & Carballo, PP. (eds.). Piscataway: IEEE Society, p. 547-555 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Composable virtual platforms for mixed-criticality embedded systems

    Beyranvand Nejad, A., 2014, 117 p.

    Research output: ThesisDissertation (TU Delft)

  47. Compositional memory systems for data intensive applications

    Molnos, AM., Heijligers, MJM., Cotofana, SD. & van Eijndhoven, JTJ., 2004, Design, automation and test in Europe; Date04 Proceedings. Gielen, G. & Figueras, J. (eds.). Piscataway: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  48. Compositional memory systems for multimedia communicating tasks

    Molnos, AM., Heijligers, MJM., Cotofana, SD. & van Eijndhoven, JTJ., 2005, Proceedings of design, automation and test in Europe 2005 (DATE 05). s.n. (ed.). Piscataway: IEEE Society, p. 932-937 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Compositional, dynamic cach management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD., Heijligers, MJM. & van Eijndhoven, JTJ., 2009, In : Journal of Signal Processing Systems: the journal of DSPtechnologies. 57, 2

    Research output: Contribution to journalArticleScientificpeer-review

  50. Compositional, dynamic cache management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD. & Heijligers, MJM., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 991-996 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Compositional, efficient caches for a chip multi-processor

    Molnos, AM., Heijligers, MJM., Cotofana, SD. & van Eijndhoven, JTJ., 2006, Design Automation & Test in Europe DATE 06. s.n. (ed.). Piscataway: IEEE Society, p. 345-350 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Compounding preprocessor for cache

    Vassiliadis, S. & Blaner, B., 2000, Priority date 2 Feb 2000

    Research output: Patent

  53. Computation-in-Memory based on Memristive Devices

    Du Nguyen, H. A., 2019, 166 p.

    Research output: ThesisDissertation (TU Delft)

  54. Computation-in-memory based parallel adder

    Du Nguyen, HA., Xie, L., Taouil, M., Nane, R., Hamdioui, S. & Bertels, K., 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH. Moritz, CA. & Rahman, M. (eds.). Piscataway: IEEE Society, p. 57-62 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. Computational Challenges of Next Generation Sequencing Pipelines Using Heterogeneous Systems

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, p. 1-4. 4 p.

    Research output: Contribution to conferenceAbstractScientific

  56. Computer architectuur, implementatie en realisatie

    Corporaal, H., 1999, ICT-zakboekje. TMA Bemelmans, PME Bra, D., M Looijen & G Oortmerssen, V. (eds.). Arnhem: Koninklijke PBNA, p. 569-663

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterProfessional

  57. Computer graphics and the MOLEN paradigm: a survey

    Calderón, H. & Vassiliadis, S., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 23-36 14 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Patent No. US 9,824,753, Priority date 21 Oct 2015

    Research output: Patent

  59. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Priority date 21 Oct 2015, Priority No. US 2017/0117041

    Research output: Patent

  60. Computing division in the electron counting paradigm using single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2006, 2006 Sixth IEEE conference on Nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. Computing division using single-electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : IEEE Transactions on Nanotechnology. 6, 4, p. 451-459 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  62. Computing periodic symmetric functions in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2005, Proceedings of international semiconductor conference (CAS, 2005). s.n. (ed.). Piscataway: IEEE Society, p. 47-50 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Conclusion: multi-core processor architectures are here to stay.

    Bertels, KLM., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 229-231 234 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  64. Concurrent engineering for intelligent simulation

    Niculiu, T. & Cotofana, SD., 2003, ECEC 2003, tenth European concurrent engineering conference, tenth anniversary conference. Baake, U., Herbst, J. & Graessler, I. (eds.). Gehnt, Belgium: Eurosis, p. 95-99 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Configurable fault-tolerance for a configurable VLIW processor

    Anjam, F. & Wong, JSSM., 2013, 9th International symposium on applied reconfigurable computing. Brisk, P., de Figueiredo Coutinho, JG. & Diniz, P. (eds.). Berlin: Springer, p. 1-12 12 p. (Lecture Notes in Computer Science; vol. 7806).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Configurable transactional memory

    Kachris, C. & Kulkarni, C., 2007, The fifteenth IEEE Symposium on Field Programmable Custom Computing Machine. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Congestion-controlled best--effort communication for network-on-chip

    van den Brand, J., Ciordas, C., Goossens, KGW. & Basten, T., 2007, Design, Automation & Test in Europe. s.n. (ed.). s.l.: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Consequences of RAM bitline twisting for test coverage

    Schanstra, I. & van de Goor, AJ., 2003, DATE'03; design automation and test in Europe. Wehn, N. & Verkest, D. (eds.). Piscataway: IEEE Society, p. 1176-1177 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Conservative application-level performance analysis through simulation of MPSoCs

    Nelson, AT., Hansson, A., Corporaal, H. & Goossens, KGW., 2010, 7th workshop on embedded systems for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. Conservative dynamic energy management for real-time dataflow applications mapped on multiple processors

    Molnos, AM. & Goossens, KGW., 2009, 12th Euromicro conference on digital system design architectures, methods and tools. Nunez, A. & Carballo, PP. (eds.). Piscataway: IEEE Society, p. 409-418 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Context aware slope based transistor-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  72. Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

    Ludovici, D., Gilabert, F., Gaydadjiev, GN. & Bertozzi, D., 2010, 3rd Intl. workshop on network on chip architectures. s.n. (ed.). Piscataway: IEEE Society, p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Control of a 3-Phase Permanent Magnet Synchronous Motor Drive Employing a Slim DC-Link

    Sivaram, S., Dong, J., van Genderen, A., Schellekens, J. & Voogt, E., 10 Jul 2019, p. 1-1. 1 p.

    Research output: Contribution to conferencePosterScientific

  74. Controlled degradation stochastic resonance in adaptive averaging cell based architectures

    Aymerich, N., Cotofana, SD. & Rubio, A., 2013, In : IEEE Transactions on Nanotechnology. 12, 6, p. 888-896 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  75. Controlling a complete hardware synthesis toolchain with LARA aspects

    Cardoso, JMP., Carvalho, T., Coutinho, JGF., Nobre, R., Nane, R., Diniz, P., Petrov, Z., Luk, W. & Bertels, KLM., 2013, In : Microprocessors and Microsystems. 37, 8, p. 1073-1089 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  76. Cost Effective Adaptive Voltage Scaling Using Path Delay Fault Testing

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2018, 2018 IEEE East-West Design and Test Symposium ( EWDTS). Danvers: IEEE, p. 1-6 6 p. 8524693

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. Cost-Efficient Fault-Tolerant Decoder for Hybrid Nanoelectronic Memories

    Haron, NZB. & Hamdioui, S., 2011, Proceedings Design, Automation and Test in Europe Conference and Exhibition (DATE 2011). Al-Hashimi, BM. & Rosenstiel, W. (eds.). Piscataway, NJ, USA: IEEE Society, p. 265-268 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. Cost-efficient SHA hardware accelerators

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 999-1008 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  79. Counter based superscalar instruction issuing

    Cotofana, SD., Juurlink, BHH. & Vassiliadis, S., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 307-315 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  80. Coupling of a reconfigurable architecture and a multithread processor core with integrated real-time

    Uhrig, S., Maier, S., Kuzmanov, GK. & Ungerer, P., 2006, Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 209-209

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Critical transistors nexus based circuit-level aging assessment and prediction

    Cucu Laurenciu, N. & Cotofana, SD., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2512-2520 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  82. Cross-layer designs architecture for LEO satellite ad hoc network

    Chang, Z. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. 5031, p. 164-176 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  83. CryoCMOS Hardware Technology: A Classical Infrastructure for a Scalable Quantum Computer

    Homulle, H., Visser, S., Patra, B., Ferrari, G., Prati, E., García Almudever, C., Bertels, K., Sebastiano, F. & Charbon, E., 2016, 2016 Proceedings of the ACM International Conference on Computing Frontiers. New York, NY: Association for Computing Machinery (ACM), p. 282-287 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Current trends in resource management of recongigurable systems

    Sabeghi, M. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 89-93 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. Custom Architecture for Immersive-Audio Applications

    Theodoropoulos, D., 2011, 160 p.

    Research output: ThesisDissertation (TU Delft)

  86. Custom architecture for multicore audio Beamforming systems

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2013, In : ACM Transactions on Embedded Computing Systems. 13, 2, p. 1-26 26 p.

    Research output: Contribution to journalArticleScientificpeer-review

  87. Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

    Hur, JY., Stefanov, TP., Wong, JSSM. & Goossens, KGW., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 59-68 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  88. Customizable Memory Schemes for Data Parallel Accelerators

    Gou, C., 2011, 190 p.

    Research output: ThesisDissertation (TU Delft)

  89. Customizable register files for multidimensional SIMD architectures

    Ciobanu, CB., 2013, 135 p.

    Research output: ThesisDissertation (TU Delft)

  90. Customized vector instruction set architecture

    Ciobanu, CB., Spinean, B., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 128-137 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. Customizing and Hardwiring On-chip Interconnects in FPGAs

    Hur, JY., 2011, Delft: Jae Young Hur. 120 p.

    Research output: ThesisDissertation (TU Delft)

  92. Customizing reconfigurable on-chip crossbar scheduler

    Hur, JY., Stefanov, TP., Wong, S. & Vassiliadis, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 210-215 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. D-SAB: a sparse matrix benchmark suite

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2003, Parallel computing technologies; seventh international conference, PaCt 2003. Malyshkin, V. (ed.). Berlin: Springer, p. 549-554 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. DAMP - Delft Altera-based multimedia platform

    Zwart, W., Eilers, J., Gaydadjiev, GN. & Cotofana, SD., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 587-594 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  95. DCT and IDCT implementations on different FPGA technologies

    Bukhari, K., Kuzmanov, GK. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 232-235 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  96. DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

    Cardoso Medeiros, G., Taouil, M., Fieback, M., Bolzani Poehls, L. M. & Hamdioui, S., 2019, Proceedings - 2019 IEEE European Test Symposium, ETS 2019: Proceedings. IEEE, Vol. 2019-May. p. 1-2 2 p. 8791517

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability

    Souza, J. D., Sartor, A. L., Carro, L., Rutzig, M. B., Wong, S. & Beck, A. C. S., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer, p. 367-378 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. DOPA: GPU-based protein alignment using database and memory access optimizations

    Hasan, L., Kentie, M. & Al-Ars, Z., 2011, In : BMC Research Notes. 4:261, p. 1-11 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  99. DPM Reduction on dual-port caches

    Hamdioui, S., van de Goor, AJ. & Rodgers, M., 2002, ETW'02: 7th IEEE European Test Workshop; Informal Digest. IEEE Society, p. 55-60 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. DRAM Specific approximation of the faulty behavior of cell defects

    Al-Ars, Z. & van de Goor, AJ., 2002, Proceedings of the 11th Asian test symposium (ATS'02). Piscataway, NJ, USA: IEEE Society, p. 98-104 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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