401 - 500 out of 1,593Page size: 100
  1. RDM+: a new mac layer real-time communication protocol

    Sabeghi, M., Naghibzadeh, M. & Bertels, K., 2007, IEEE Samoff symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. RACE: A software-based fault tolerance scheme for systematically transforming ordinary algorithms to robust algorithms

    Yeh, C-H., Parhami, B., Varvarigos, EA. & Varvarigou, TA., 2001, Proceedings 15th international parallel and distributed processing symposium. Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Quipu: a statistical model for predicting hardware resources

    Meeuws, RJ., Ostadzadeh, SA., Galuzzi, C., Sima, VM., Nane, R. & Bertels, KLM., 2013, In : ACM Transactions on Reconfigurable Technology and Systems. 6, 1, p. 1-25 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Queue management in network processors

    Papaefstathiou, I., Orphanoudakis, T., Kornaros, G., Kachris, C., Mavroidis, I. & Nikologiannis, A., 2005, Proceedings of Design, automation and test in Europe 2005 (DATE 05). s.n. (ed.). Piscataway: IEEE Society, p. 112-117 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Quasi on-line testing of embedded random access memory

    Demidenko, S., Lord, N., van de Goor, AJ. & Piuri, V., 2002, MPCS '02 Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  6. Quantum accelerated computer architectures

    Riesebos, L., Fu, X., Moueddenne, A. A., Lao, L., Varsamopoulos, S., Ashraf, I., Van Someren, J., Khammassi, N., Almudever, C. G. & Bertels, K., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Yasuura, H., Miyanaga, Y. & Kiya, H. (eds.). Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. 4 p. 8702488

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Quantum Control Architecture: Bridging the Gap between Quantum Software and Hardware

    Fu, X., 2018, 156 p.

    Research output: ThesisDissertation (TU Delft)

  8. Quantum Computer Architecture: a full-stack overview

    Bertels, K. (Guest ed.), Hogaboam, J. W. & Almudever, C. G. (Guest ed.), 2019, In : Microprocessors and Microsystems. 66, p. 21-66

    Research output: Contribution to journalSpecial issueScientificpeer-review

  9. Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators

    Bertels, K., Sarkar, A., Hubregtsen, T., Serrao, M., Mouedenne, A. A., Yadav, A., Krol, A. & Ashraf, I., 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). IEEE, p. 1-6 9116502

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Quantitative prediction for early design space exploration in Delft workbench: an outlook

    Meeuws, RJ., Sigdel, K., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 311-316 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Quantitative hardware prediction modeling for hardware/software co-design

    Meeuws, RJ., 2012, Delft. 187 p.

    Research output: ThesisDissertation (TU Delft)

  12. Quantitative application data flow characterization for heterogeneous multicore architectures

    Ostadzadeh, SA., 2012, Delft. 235 p.

    Research output: ThesisDissertation (TU Delft)

  13. Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability

    Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P., Catthoor, F. & Dehaene, W., 2016, Proceedings - IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016). Taskin, B. & Ghosal, P. (eds.). Los Alamitos, CA: IEEE, p. 725-730 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Quality versus cost analysis for 3D Stacked ICs

    Taouil, M., Hamdioui, S. & Marinissen, EJ., 2014, Proceedings - 32nd IEEE VLSI Test Symposium. Thibeault, C. (ed.). Los Alamitos, CA, USA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Qualitative company performance evaluation: linear discriminant analysis and neural network models

    Bertels, KLM., Jacques, JM., Neuberg, L. & Gatot, L., 1999, In : European Journal of Operational Research. 115, 3, p. 608-615 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. QX: A high-performance quantum computer simulation platform

    Khammassi, N., Ashraf, I., Fu, X., García Almudever, C. & Bertels, K., 2017, Proceedings of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, p. 464-469 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. QUAD-quantitative usage analysis of data

    Ostadzadeh, SA., Meeuws, RJ. & Bertels, KLM., 2010.

    Research output: Contribution to conferencePosterScientific

  18. QUAD - a memory access pattern analyser

    Ostadzadeh, SA., Meeuws, RJ., Galuzzi, C. & Bertels, K., 2010, 6th Intl symposium, ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Heidelberg: Springer, p. 269-281 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Pushing Big Data into Accelerators: Can the JVM Saturate Our Hardware?

    Peltenburg, J. W., Hesam, A. & Al-Ars, Z., 2017, High Performance Computing: ISC High Performance 2017 International Workshops, DRBSD, ExaComm, HCPM, HPC-IODC, IWOPH, IXPUG, P^3MA, VHPC, Visualization at Scale, WOPSSS, Revised Selected Papers. Kunkel, J. M., Yokota, R., Taufer, M. & Shalf, J. (eds.). Cham: Springer, p. 220-236 16 p. (Lecture Notes in Computer Science; vol. 10524).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Protective redundancy overhead reduction using instruction vulnerability factor

    Borodin, D. & Juurlink, B., 2010, 2010 ACM interl. conf. on Computing Frontiers. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 319-326 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Programming the sandbridge multithraeded processor

    Jinturkar, S., Glossner, CJ. & Moudgill, M., 2003, ISPC conference proceedings; international signal processing conference. s.n. (ed.). X-CD Business Technologies, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  22. Profiling-based state assignment for low power dissipation

    Eggermont, R., Cotofana, SD. & Lageweg, CR., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 377-384 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  23. Profiling of symmetric -encryption algorithms for a novel biomedical-implant architecture

    Strydis, C., Zhu, D. & Gaydadjiev, GN., 2008, 2008 Computing Frontiers. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 231-240 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Profiling of lossless-compression algorithms for a novel biomedical-implant

    Strydis, C. & Gaydadjiev, GN., 2008, ESWEEK 2008 Compilation Proceedings. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 109-114 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Profiling bluetooth and Linux on the Xilinx virtex II pro

    Campos Soares Borrego, F. & Wong, S., 2006, 9th Euromicro Conference on Digital System Design Architecture, Methods and Tools DSD 2006. Muthukumar, V. (ed.). Los Alamitos: IEEE Society, p. 229-235 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Profile-guided application partitioning for heterogeneous reconfigurable platforms

    Ostadzadeh, SA., Meeuws, RJ., Ashraf, I., Galuzzi, C. & Bertels, KLM., 2012, 16th International symposium on computer architecture and digital systems. s.n. (ed.). s.l.: s.n., p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs

    Mirzoyan, D., Akesson, B. & Goossens, KGW., 2014, In : ACM Transactions on Embedded Computing Systems. 13, 2s, p. 1-24 24 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

    Mirzoyan, D., Akesson, B. & Goossens, KGW., 2012, 13th International symposium on quality electronic design. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Preliminary analyses of the cell BE processor limitations for sequence alignment applications

    Isaza, S., Sanchez, F., Gaydadjiev, GN., Ramirez, A. & Valero, M., 2008, In : Lecture Notes in Computer Science. LNCS5114, p. 53-64 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. Predictive Genome Analysis Using Partial DNA Sequencing Data

    Ahmed, N., Bertels, K. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 119-124 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Predator: a predictable SDRAM memory controller

    Akesson, B., Goossens, KGW. & Ringhofer, M., 2007, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 251-256 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. PowerPC compiler backend for the molen programming paradigm

    Panainte, E., Bertels, KLM. & Vassiliadis, S., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 121-126 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

    Goossens, S., Chandrasekar, K., Akesson, B. & Goossens, K., 2016, In : IEEE Transactions on Computers. 65, 6, p. 1882-1895 14 p., 7169527.

    Research output: Contribution to journalArticleScientificpeer-review

  34. Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms

    Houtgast, E., Sima, V., Marchiori, G., Bertels, K. & Al-Ars, Z., 2016, p. 1-1. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  35. Power-Efficiency Analysis of Accelerated BWA-MEM Implementations on Heterogeneous Computing Platforms

    Houtgast, E. J., Sima, V-M., Marchiori, G., Bertels, K. & Al-Ars, Z., Dec 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Athanas, P., Cumplido, R., Feregrino, C. & Sass, R. (eds.). Danvers, MA: IEEE, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Power versus quality trade-offs for adaptive real-time applications

    Nelson, AT., Akesson, B., Molnos, AM., te Pas, SF. & Goossens, KGW., 2012, IEEE Symposium on embedded systems for real-time multimedia. s.n. (ed.). s.l.: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profile

    Altman, ER., Glossner, CJ., Hokenek, E., Meltzer, D. & Moudgill, M., 2003, Patent No. US 2002/0112193 A1, Priority date 15 Aug 2002

    Research output: Patent

  38. Power consumption evaluation for biological sequence alignment

    Hasan, L. & Al-Ars, Z., 2010, ProRISC 2010. French, PJ. (ed.). Nederland: STW, p. 42-46 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. Power and performance profiling of lossless compression algorithms in ultra-low-power embedded cores

    Strydis, C. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 375-379 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Power analysis of parallel CA-CFAR FPGA design

    Kyovtorov, VA., Kabakchiev, H. & Kuzmanov, GK., 2010, 11th intl. radar symposium. s.n. (ed.). Piscataway: IEEE Society, p. 305-308 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Power Minimisation for Real-time Dataflow Applications

    Nelson, AT., Moreira, O., Molnos, AM., Stuijk, S., Nguyen, BT. & Goossens, KGW., 2011, Proceedings of the International Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 117-124 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Post-bond interconnect test and diagnosis for 3-D memory stacked on logic

    Taouil, M. & Hamdioui, S., 2015, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 34, 11, p. 1860-1872 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  43. Porting and Benchmarking of BWAKIT Pipeline on OpenPOWER Architecture

    Kathiresan, N., Al-Ali, R., Jithesh, P., Narayanasamy, G. & Al-Ars, Z., 2018, High Performance Computing : ISC High Performance 2018 International Workshops, Revised Selected Papers. Yokota, R., Weiland, M., Shalf, J. & Alam, S. (eds.). Cham: Springer, p. 402-410 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 11203 ).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Port interference faults in two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 1999, Proceedings. S.l.: IEEE Society, p. 1001-1010 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Polymorphic processors: how to expose arbitrary hardware functionality to programmers

    Vassiliadis, S., Wong, JSSM., Gaydadjiev, GN. & Bertels, KLM., 2003, The IEE FPGA developers' forum. s.n. (ed.). London: IEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Polymorphic instruction set computers

    Kuzmanov, GK. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 217-254 378 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  47. Polymorphic architectures - from media processing to supercomputing

    Kuzmanov, GK., 2009, Proceedings of the international conference on computer systems and technologies and workshop for PhD students in computing. Rachev, B. & Smrikarov, A. (eds.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Polymorphic AES encryption implementation

    Fernades Chaves, R., Sousa, L., Kuzmanov, GK. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 343-351 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  49. Planar Sensor Structures for Whole Blood Viscosity Measurements

    Firouzian, A., Tanase, D., Iliev, BP., Chang, Z., Van Duyl, WA. & French, PJ., 2006, Planar Sensor Structures for Whole Blood Viscosity Measurements. s.n. (ed.). Veldhoven, The Netherlands.: SAFE, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  50. Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

    Wu, L., Rao, S., Cardoso Medeiros, G., Taouil, M., Marinissen, E. J., Yasin, F., Couet, S., Hamdioui, S. & Kar, G. S., 2019, 2019 IEEE European Test Symposium (ETS): Proceedings. Danvers: IEEE, p. 1-6 6 p. 8791518

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Periodic symmetric functions and addition related arithmetic operations in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 247-252 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  52. Performance-oriented fault tolerance in computing systems

    Borodin, D., 2010, Delft. 138 p.

    Research output: ThesisDissertation (TU Delft)

  53. Performance scalability of multimedia instruction set extensions

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2002, Euro-Par 2002 Parallel processing. Monien, B. & Feldmann, R. (eds.). Berlin: Springer, p. 849-861 13 p. (Lecture Notes in Computer Science; vol. 2400).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. Performance relevant issues for parallel computation models

    Juurlink, BHH. & Rieping, I., 2001, PDPTA'2001: proceedings. Vol 4. S.l.: CSREA, p. 1841-1847 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. Performance of the complex streamed instruction set on image processing kernels

    Tcheressiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, H., 2001, Euro-Par 2001: proceedings. R Sakellariou & ... [et Al] (eds.). Berlin: Springer, p. 678-686 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Performance improvement of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 211-214 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Performance improvement of multimedia kernels by alleviating overhead instructions on SIMD devices

    Shahbahrami, A. & Juurlink, B., 2009, In : Lecture Notes in Computer Science. 5737, p. 389-407 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  58. Performance impact of misaligned accesses in SIMD extensions

    Shahbahrami, A., Juurlink, BHH. & Vassiliadis, S., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 334-342 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. Performance guarantees in partially buffered crossbar switches

    Skalis, N. & Mhamdi, LL., 2010, IEEE Globecom 2010 proceedings. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. Performance evaluation of real-time message delivery in RDM algorithm

    Mirshokraie, S., Sabeghi, M., Naghibzadeh, M. & Bertels, K., 2007, Third Intl. conference on Networking and services. s.n. (ed.). Piscataway: IEEE Society, p. 74-79 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

    Alvarez, M., Ramirez, A., Valero, M., Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2009, Proceedings of the 4th Colombian Computing Conference ( Congreso Colombiano de Computacion). s.n. (ed.). s.l.: s.n., p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

    Alvarez, M., Ramirez, A., Valero, M., Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2009, In : Avances en Sistemas e Informatica. 6, 1, p. 219-228 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  63. Performance evaluation of interleaved multithreading in a VLIW architecture

    Suijkerbuijk, S., Stravers, P., Vassiliadis, S. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 153-160 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  64. Performance evaluation of an adaptive FPGA for network applications

    Kachris, C. & Vassiliadis, S., 2006, Proceedings seventeenth IEEE International workshop on Rapid System Prototyping. s.n. (ed.). Piscataway: IEEE Society, p. 54-60 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Performance evaluation for a quasi-synchronous packet radio network (QSPNET)

    Banerjee, A., Iltis, RA. & Varvarigos, EA., 2001, In : IEEE - ACM Transactions on Networking. 9, 5, p. 567-578 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  66. Performance comparison of SIMD implementations of the discrete wavelet transform

    Shahbahrami, A., Juurlink, BHH. & Vassiliadis, S., 2005, Proceedings of the 16th IEEE International conference on Application-Specific Systems Architectures and Processors (ASAP). Vassiliadis, S., Dimopoulos, N. & Rajopadhye, S. (eds.). Los Alamitos: IEEE Society, p. 393-398 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Performance comparison between linear RVE and linear systolic array implementations of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 451-455 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Performance benefits of relaxed memory consistency for process network applications

    Bos, R. & Juurlink, BHH., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 10-16 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  69. Performance benefits for special-purpose instructions in the CSI architecture

    Cheresiz, D., Juurlink, BHH. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 236-241 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  70. Performance and bandwidth optimization for biological sequence alignment

    Hasan, L., Al-Ars, Z., Taouil, M. & Bertels, KLM., 2010, 5th Intl. design and test workshop. Elahi, I., Ivanov, A., Zorian, Y. & Salem, A. (eds.). Piscataway: IEEE Society, p. 155-160 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Performance analysis of RR and FQ algorithms in reconfigurable routers

    Ludovici, D. & Wong, JSSM., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 306-312 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs

    Hur, JY., Goossens, KGW. & Mhamdi, LL., 2008, 16th IFIP/IEEE Intl. Conference on Very Large Scale Integration. s.l. (ed.). s.n., p. 224-232 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Pel reconstruction on FPGA-augmented TriMedia

    Sima, M., Cotofana, SD., Vassiliadis, S., van Eijndhoven, JTJ. & Vissers, KA., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 6, p. 622-635 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. Pauli Frames for Quantum Computer Architectures

    Riesebos, L., Fu, X., Varsamopoulos, S., García Almudever, C. & Bertels, K., 2017, Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Aitken, R. & Li, Z. (eds.). New York: Association for Computing Machinery (ACM), p. 1-6 76

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. Partilially reconfigurable point-to-point FPGA interconnects

    Hur, JY., Wong, S. & Vassiliadis, S., 2008, In : International Journal of Electronics. 95, 7

    Research output: Contribution to journalArticleScientificpeer-review

  76. Partially reconfigurable point-to-point interconnects in virtex-II pro FPGAs

    Hur, JY., Wong, S. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 49-60 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  77. Parasitic memory effect in CMOS SRaMs

    Irobi, IS., Al-Ars, Z. & Renovell, M., 2010, 5th Intl. design and test workshop. Elahi, I., Ivanov, A., Zorian, Y. & Salem, A. (eds.). Piscataway: IEEE Society, p. 134-142 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. Parametrizing Multicore Architectures for Multiple Sequence Alignment

    Isaza Ramirez, S., Sanchez, F., Cabarcas, F., Ramirez, A. & Gaydadjiev, GN., 2011, ACM International Conference on Computing Frontiers 2011. Cascaval, C., Prasanna, V. & Trancoso, P. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM

    Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 1 Jun 2019, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 6, p. 1308-1321 14 p., 8678671.

    Research output: Contribution to journalArticleScientificpeer-review

  80. Parameter optimization of the adaptive MVDR QR-based beamformer for jamming and multipath suppression in GPS/GLONASS receivers

    Behar, V., Kabakchiev, C., Gaydadjiev, GN., Kuzmanov, GK. & Ganchosov, PN., 2009, 16th Saint Petersburg international conference on integrated navigation systems. s.n. (ed.). s.l.: s.n., p. 325-334 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Parallellism support in SIMD/VLIW image processing architectures

    Fatemi, H., Corporaal, H., Basten, T., Kleihorst, RP. & Jonker, PP., 2005, ASCI 2005: Proceedings of the eleventh annual conference of the advanced school for computing and imaging. Krose, BJA., Bos, HJ., Hendriks, EA. & Heijnsdijk, JWJ. (eds.). Delft: ASCI, p. 291-296 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. Parallelization of variable rate decompression through metadata

    Noordsij, L., Vlugt, S. V. D., Bamakhrama, M. A., Al-Ars, Z. & Lindstrom, P., 2020, Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. Daneshtalab, M., Francesco, L. & Sjödin, M. (eds.). Institute of Electrical and Electronics Engineers (IEEE), p. 245-252 8 p. 9092414

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Parallelism utilization in embedded reconfigurable computing systems: a survey of recent trends

    Ostadzadeh, SA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 338-348 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Parallel scalability of video decoders

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, In : Journal of V LSISignal Processing. p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  85. Parallel multiple-symbol variable-length decoding

    Nikara, J., Vassiliadis, S., Takala, J., Sima, M. & Liuha, P., 2002, ICCD 2002; Proceedings 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors. Werner, B. (ed.). Piscataway, NJ. USA: IEEE Society, p. 126-131 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. Parallel merge sort on a binary tree on-chip network

    Wong, S., Vassiliadis, S. & Hur, JY., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 365-368 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  87. Parallel computer architecture and instruction-level parallelism

    Vassiliadis, S., Dimopoulos, N., Collard, JF. & Bode, A., 2003, In : Lecture Notes in Computer Science. p. 541-542 2 p.

    Research output: Contribution to journalArticleScientific

  88. Parallel computer architecture

    Müller, S., Stenström, P., Valero, M. & Vassiliadis, S., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 537-538 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  89. Parallel algorithms on the rotation-exchange network - a trivalent variant of the star graph

    Yeh, CH. & Varvarigos, EA., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 303-309 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  90. Parallel Scalability of H.264

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Alvarez, M., Juurlink, B. & Ramirez, A., 2008, First Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG-1). s.n. (ed.). s.l., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture

    Haron, A., Yu, J., Nane, R., Taouil, M., Hamdioui, S. & Bertels, K., 2016, 2016 International Conference on High Performance Computing & Simulation (HPCS): 14th Annual Meeting. Piscataway: IEEE, p. 759-766 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Parallel H.264 decoding on an embedded multicore processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Terechko, A., Hoogerbrugge, J., Alvarez, M. & Ramirez, A., 2009, In : Lecture Notes in Computer Science. 5409, p. 404-418 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  93. Parallel FPGA design of CA CFAR algorithm

    Kyovtorov, VA., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 470-474 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. Parallel Access Schemes for Polymorphic Register Files: Motivation Study

    Ciobanu, CB., Kuzmanov, GK., Ramirez, A. & Gaydadjiev, GN., 2011, Proceedings 7th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems. de Bosschere et al, K. (ed.). Ghent, Belgium: HiPEAC, p. 127-130 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Packet pre-filtering for network intrusion detection

    Sourdis, I., Dimopoulos, V., Pnevmatikatos, DN. & Vassiliadis, S., 2006, 2006 ACM/IEEE symposium on architectures for networking and communications systems. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 183-192 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. PUMA: Placement Unification with Mapping and guaranteed throughput Allocation on an FPGA Using A Hardwired NoC

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 88-98 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. PPM recuction on embedded memories in system on chip

    Hamdioui, S., Al-Ars, Z., Jimenez, J. & Calero, J., 2007, 12th IEEE European Test Symposium. Lisa O'Conner (ed.). Piscataway: IEEE Society, p. 85-90 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. PISC: Polymorphic instruction set computers

    Vassiliadis, S., Kuzmanov, GK., Wong, S., Panainte, E., Gaydadjiev, GN., Bertels, K. & Cheresiz, D., 2006, Reconfigurable Computing: Architectures and Applications. Bertels, K., Cardoso, J. & Vassiliadis, S. (eds.). Heidelberg: Springer, p. 274-286 13 p. (Lecture Notes in Computer Science; vol. 3985).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. PBC: a partially buffered crossbar packet switch

    Mhamdi, LL., 2009, In : IEEE Transactions on Computers. 58, 11, p. 1568-1581 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  100. Optimizing test length for soft faults in DRAM devices

    Al-Ars, Z., Hamdioui, S. & Gaydadjiev, GN., 2007, 25th IEEE VLSI Test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 59-66 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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