501 - 600 out of 1,585Page size: 100
  1. DRAM fault analysis and test generation

    Al-Ars, Z., 2005, s.l.: s.n.. 281 p.

    Research output: ThesisDissertation (TU Delft)

  2. DRAM-specific space of memory tests

    Al-Ars, Z., Hamdioui, S., van de Goor, AJ., Gaydadjiev, GN. & Vollrath, J., 2006, International Test Conference 2006. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

    Nane, R., Sima, VM., Olivier, B., Meeuws, RJ., Yankova, YD. & Bertels, KLM., 2012, 22nd International conference on field programmable logic and applications. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. DWARV: Delftworkbench automated reconfigurable VHDL generator

    Yankova, YD., Bertels, K., Kuzmanov, GK., Gaydadjiev, GN., Lu, Y. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 697-701 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Data cache optimization in multimedia applications

    Molnos, AM., Heijligers, MJM., Cotofana, SD., van Eijndhoven, JTJ. & Mesman, SD., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 529-532 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Data locality optimization based on comprehensive knowledge of the cache miss reason: a case study with DWT

    Tao, J. & Shahbahrami, A., 2008, 10th IEEE intl. Conf. on High Performance Computing and Communications. s.n. (ed.). s.l.: IEEE Society, p. 304-311 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Data path configuration time reduction for run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A., Sabeghi, M., Bertels, K. & Gaydadjiev, GN., 2009, The 2009 international conference on engineering of reconfigurable systems & algorithms. Plaks, T. (ed.). s.l.: CSREA Press, p. 323-327 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Data structure, method and system for address lookup

    Sourdis, I., Smet de, R., Stefanakis, G. & Gaydadjiev, GN., 2010, Patent No. NL 2002799, Priority date 26 Oct 2010

    Research output: Patent

  9. Data- and Task Parallel Image Processing on a Mixed SIMD-ILP Platform using Skeletons and Asynchronous RPC

    Caarls, W., Jonker, PP. & Corporaal, H., 2004, Proc. 5th PROGRESS Symposium on Embedded Systems. M. Schweizer (ed.). Utrecht: STW, p. 27-34 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Database Acceleration on FPGAs

    Fang, J., 2019, 93 p.

    Research output: ThesisDissertation (TU Delft)

  11. Datalife time analysis in RDM+ real-time communication protocol

    Mirshokraie, S., Sabeghi, M., Bertels, K. & Naghibzadeh, M., 2007, 2007 IEEE international conference on signal processing and communications. s.n. (ed.). Piscataway: IEEE Society, p. 540-543 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Deadline vs. laxity as a decision parameter in fuzzy real-time scheduling

    Sabeghi, M., Bertels, K. & Naghibzadeh, M., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 354-358 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Debugging distributed-shared-memory communication at multiple granularities in network on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 3-12 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Debugging distributed-shared-memory communication at multiple granularities in networks on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE international symposium on networks-on-chip. s.n. (ed.). Piscataway: IEEE Society, p. 3-12 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms

    Molnos, AM., Beyranvand Nejad, A., Nguyen, BT., Cotofana, SD. & Goossens, KGW., 2012, 15th Intl.Workshop on software and compilers for embedded systems. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Defect and Fault Modeling Framework for STT-MRAM Testing

    Wu, L., Rao, S., Taouil, M., Cardoso Medeiros, G., Fieback, M., Marinissen, E. J., Kar, G. S. & Hamdioui, S., 17 Dec 2019, In : IEEE Transactions on Emerging Topics in Computing. 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Defect oriented testing of the strap problem under process variations in DRAMs

    Al-Ars, Z., Hamdioui, S., van de Goor, AJ. & Mueller, G., 2008, Proc. International Test Conference 2008. s.n. (ed.). Washington DC: ITC, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. Degradation analysis of high performance 14nm FinFET SRAM

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 1 Mar 2018, 2018 Design, Automation Test in Europe Conference Exhibition (DATE). p. 201-206 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Degradation stochastic resonance (DSR) in AD-AVG architectures

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, 12th IEEE International conference on nanotechnology. s.n. (ed.). New York: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. Delay evaluation of high speed data-path circuits based on threshold logic

    Celinski, P., Abbott, D. & Cotofana, SD., 2004, Integrated circuit and system design; Power and timing modeling, optimization and simulation. Macii, E., Paliouras, V. & Koufopavlou, O. (eds.). Berlin: Springer, p. 899-906 8 p. (Lecture Notes in Computer Science; vol. 3254).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Delft-Java dynamic translation

    Glossner, CJ. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 57-61 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Dependable Network Topologies

    Joshi, P., 2019, 81 p.

    Research output: ThesisDissertation (TU Delft)

  23. Dependable multicore architectures at nanoscale: The view from Europe

    Ottavi, M., Pontarelli, S., Gizopoulos, D., Paschalis, A., Bolchini, C., Michael, MK., Anghel, L., Tahoori, M., Reviriego, P., Bringmann, O., Izosimov, V., Manhaeve, H., Strydis, C. & Hamdioui, S., 2015, In : IEEE Design & Test of Computers. 32, 2, p. 17-28 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. Deriving resource efficient designs using the REFLECT aspect-oriented approach

    Coutinho, JGF., Cardoso, JMP., Carvalho, T., Nobre, R., Bhattacharya, S., Diniz, PC., Fitzpatrick, L. & Nane, R., 2013, International symposium ARC. Coutinho, JGF., Brisk, P. & Diniz, PC. (eds.). Heidelberg: Springer, p. 226-228 3 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Design & Technology of Integrated Systems in Nanoscala era

    Hamdioui, S. & Orailoglu, A., 2007, Piscataway: IEEE Society. 260 p.

    Research output: Book/ReportBookProfessional

  26. Design & algorithms for packet and content inspection

    Sourdis, I., 2007, Delft: s.l.. 162 p.

    Research output: ThesisDissertation (TU Delft)

  27. Design alternatives for parallel saturating multioperand adders

    Balzola, PI., Schulte, MJ., Ruan, J., Glossner, CJ. & Hokenek, E., 2001, Proceedings 2001 IEEE International conference on Computer design: VLSI in computers & Processors. Piscataway: IEEE Society, p. 172-178 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Design and experimental results of a CMOS flip-flop featuring embedded threshold logic

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2003, ISCAS 2003; Proceedings of the 2003 IEEE international symposium on circuits and systems. Piscataway: IEEE Society, p. 253-256 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Design and implementation of an operating system for composable processor sharing

    Hansson, A., Molnos, AM., Nelson, AT., Ambrose, JA. & Goossens, KGW., 2011, In : Microprocessors and Microsystems. 35, p. 246-260 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. Design and implementation of reliable wireless sensor networks-a case study in commuter trains

    Kootkar, S. & Al-Ars, Z., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 303-306 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Design and performance evaluation of an adaptive FPGA for network applications

    Kachris, C., Wong, S. & Vassiliadis, S., 2009, In : Microelectronics Journal. 40, 7, p. 1103-1110 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  32. Design and test of integrated circuits in Nano era: what is next?

    Hamdioui, S., 2008.

    Research output: Contribution to conferenceAbstractScientific

  33. Design challenges in security processing

    Wu, Y. & Wong, JSSM., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 189-194 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  34. Design considerations for a domain specific vector microarchitecture

    Spinean, B., Ciobanu, CB., Kuzmanov, GK. & Gaydadjiev, GN., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 178-184 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Design considerations of a multiple inner product and accumulate vector functional unit

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 481-485 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  36. Design dependent SRAM PUF robustness analysis

    Cortez, AMMO., Hamdioui, S. & Ishihara, R., 2015, Proceedings - 16th IEEE Latin-American Test Symposium. Champac, V. & Zorian, Y. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Design methodology for single electron based building blocks

    Meenderinck, CH., Lageweg, CR. & Cotofana, SD., 2005, Proceedings of 2005 5th IEEE Conference on Nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 271-274 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Design of 100 µW wireless sensor nodes on energy scavengers for biomedical monitoring

    Yseboodt, L., De Nil, M., Huisken, J., Berekovic, M., Zhao, Q., Bouwens, F. & van Meerbergen, J., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 385-395 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. Design of a pipelined and parameterized VLIW processor: r-VEX v.2.0

    Seedorf, RAE., Anjam, F., Brandon, AAC. & Wong, JSSM., 2012, 6th HiPEAC workshop on reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Design of a web switch in a reconfigurable platform

    Kachris, C. & Vassiliadis, S., 2006, 2006 ACM/IEEE symposium on architectures for networking and communications systems. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 31-40 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

    Ludovici, D., Strano, A., Gaydadjiev, GN., Benini, L. & Bertozzi, D., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 679-684 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Design space exploration of configuration manager for network processing applications

    Kachris, C. & Vassiliadis, S., 2007, International conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Glossner, J. Blume, H., G. G. (ed.). Piscataway: IEEE Society, p. 34-40 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Design trade-offs in customized on-chip crossbar schedulers

    Hur, JY., Wong, S. & Stefanov, TP., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  44. Design tradeoffs for an embedded open GL-compliant hardware rasterizer

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2003, Proceedings of ProRISC 2003. Utrecht: STW, p. 49-55 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Designing domain-specific processors

    Arnold, M. & Corporaal, H., 2001, CODES 2001: proceedings. New York: Association for Computing Machinery (ACM), p. 61-66 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Designing regular network-on-chip topologies under technology, architecture and software constraints

    Gilabert, F., Ludovici, D., Medardoni, S., Bertozzi, D., Benini, L. & Gaydadjiev, GN., 2009, 2009 International workshop on multi-core computing systems. s.n. (ed.). Piscataway: IEEE Society, p. 681-687 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. DetLock: portable and efficient deterministic execution for shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 5th International workshop on multi-core computing systems. s.n. (ed.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Detecting faults in peripheral circuits and an evaluation of SRAM tests

    van de Goor, AJ., Hamdioui, S. & Wadsworth, R., 2004, Proceedings International Test Conference 2004. Washington, D.C.: International Test Conference, p. 114-123 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Detecting intra-word faults in word-oriented memories

    Hamdioui, S., van de Goor, AJ. & Rodgers, M., 2003, 21th IEEE VLSI test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 241-247 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Detecting memory faults in the presence of bit line coupling in SRAM devices

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2010, Intl. test conference 2010. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. Detecting unique faults in multi-port SRAMs

    Hamdioui, S., van de Goor, AJ., Eastwick, D. & Rodgers, M., 2001, Proceedings. DC Young (ed.). Los Alamitos: IEEE, p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs

    Augusto da Silva, F., Bagbaba, A. C., Sartoni, S., Cantoro, R., Reorda, M. S., Hamdioui, S. & Sauer, C., 2020, 2020 IEEE European Test Symposium (ETS): Proceedings. IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. Determining a coverage mask for a pixel

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, IPC No. Nokia Corporation/niet eerder opgevoerd, sb, Patent No. US 2004/0207642 A1, Priority date 21 Oct 2004

    Research output: Patent

  54. Determining the criticality of processes in Kahn process networks for design space exploration

    Hofstee, D. & Juurlink, BHH., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 292-297 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  55. Developing a retargetable compiler: some preliminary results

    Panainte, E., Bertels, KLM. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  56. Developing and implementing peak detection for real-time image registration

    Ma, M., van Genderen, AJ. & Beukelman, P., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 647-652 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  57. Device aging: A reliability and security concern

    Kraak, D., Taouil, M., Hamdioui, S., Weckx, P., Catthoor, F., Chatterjee, A., Singh, A., Wunderlich, H. & Karimi, N., 1 May 2018, 2018 IEEE 23rd European Test Symposium (ETS). p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. Device-Aware Test: A New Test Approach Towards DPPB Level

    Fieback, M., Wu, L., Cardoso Medeiros, G., Aziza, H., Rao, S., Marinissen, E. J., Taouil, M. & Hamdioui, S., 9 Nov 2019, 2019 IEEE International Test Conference (ITC). IEEE, 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. DfT schemes for resistive open defects in RRAMs

    Haron, NZB. & Hamdioui, S., 2012, Design, automation & test in Europe conference & exhibition. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. Digital analysis of papers for the authentication and dating of art

    Pourebrahimi, B., Van Der Lubbe, J. C. A. & Dietz, G., 2010, Proceedings of the 12th IASTED International Conference on Signal and Image Processing, SIP 2010. p. 93-100 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. Digital to analog conversion performed in single electron technology

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, IEEE-NANO 2001: proceedings. Piscataway: IEEE Society, p. 105-110 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. Diminished-1 Fermat Number Transform for Integer Convolutional Neural Networks

    Baozhou, Z., Ahmed, N., Peltenburg, J., Bertels, K. & Al-Ars, Z., 2019, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA). Guan, S-U., Zhang, K. & Cao, J. (eds.). Piscataway, NJ, USA: IEEE, p. 47-52 6 p. 8713250

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Direct and transposed sparse matrix-vector multiplication

    Cotofana, SD., Stathis, PT. & Vassiliadis, S., 2002, MPCS '02 Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  64. Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface

    Marinissen, EJ., De Wachter, B., Smith, K., Kiesewetter, J., Taouil, M. & Hamdioui, S., 2014, Proceedings 2014 IEEE International Test Conference. Purtell, M. & Mitra, S. (eds.). Washington, DC, USA: ITC & IEEE, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Distributed parallel scheduling algorithms for high speed virtual output queuing switches

    Mhamdi, LL. & Hamdi, M., 2009, IEEE symposium on computers and communications 2009. s.n. (ed.). Piscataway: IEEE Society, p. 944-949 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Distributed processing array with component processors performing customized interpretation of instructions

    Pechanek, GG., Larsen, LD., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 3 Oct 2000

    Research output: Patent

  67. Drift-free video coding for privacy protected video scrambling

    Choupani, R., Wong, S. & Tolun, M., 2016, 10th International Conference on Information, Communications and Signal Processing, ICICS 2015. Piscataway, NJ: IEEE, p. 1-5 5 p. 7459830

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Dynamic FPGA reconfigurations with run-time region delimitation

    Bok van der, K., Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & van Genderen, AJ., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 201-207 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-issue VLIW Processor

    Sartor, A. L., Becker, P. H. E., Hoozemans, J., Wong, S. & Beck, A. C. S., 2018, In : IEEE Transactions on Multi-Scale Computing Systems. 4, 3, p. 327-339 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  70. Dynamic bitstream length scaling energy effective stochastic LDPC decoding

    Marconi, T. & Cotofana, SD., 2015, Proceedings of the 25th Great Lakes Symposium on VLSI, GLSVLSI 2015. Coskun, AK. & Margala, M. (eds.). New York: Association for Computing Machinery (ACM), p. 245-248 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Dynamic faults in random-access-memories: concept, fault models and tests

    Hamdioui, S., Al-Ars, Z., van de Goor, AJ. & Rodgers, M., 2003, In : Journal of Electronic Testing: theory and applications. 19, 2, p. 195-205 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  72. Dynamic hardware reconfigurations: performance impact for MPEG2

    Panainte, E., Bertels, K. & Vassiliadis, S., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 284-292 9 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Dynamic profiling framework in the Delft workbench

    Ostadzadeh, SA. & Bertels, KLM., 2010.

    Research output: Contribution to conferencePosterScientific

  74. Dynamic techniques to reduce memory traffic in embedded systems

    Juurlink, BHH. & de Langen, PJ., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 192-201 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. Dynamic workload peak detection for slack management

    Milutinovic, A., Goossens, KGW. & Smit, GJM., 2009, 2009 international symposium on system-on-chip proceedings. s.n. (ed.). Piscataway: IEEE Society, p. 42-47 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Dynamically reconfigurable register file for a softcore VLIW processor

    Wong, JSSM., Anjam, F. & Nadeem, MF., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. ECC design for fault-tolerant crossbar memories: a case study

    Haron, NZB., Hamdioui, S. & Ahyadi, Z., 2010, 5th Intl. design and test workshop. Elahi, I., Ivanov, A., Zorian, Y. & Salem, A. (eds.). Piscataway: IEEE Society, p. 61-666 606 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. ERA-Embedded reconfigurable architectures

    Wong, JSSM., Carro, L., Rutzig, M., Mota Mattos, D., Giorgi, R., Puzovic, N., Kaxiras, S., Cintra, M., Desoli, G., Gai, P., McKee, S. & Zaks, A., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 239-260 290 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  79. ESL design of customizable real-time neuron networks

    van Eijk, M., Galuzzi, C., Zjajo, A., Smaragdos, G., Strydis, C. & van Leuken, TGRM., 2014, Proceedings - 2014 IEEE Biomedical Circuits and Systems Conference. Carrara, S. & Enz, C. (eds.). Piscataway, NJ, USA: IEEE Society, p. 671-674 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. ESRAM Reliability: Why is it still not optimally solved?

    Kraak, D., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 2020, Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020. Piscataway, NJ, USA: Institute of Electrical and Electronics Engineers (IEEE), 6 p. 9081145

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Early DNA Variant Calling Using Incomplete DNA Datasets

    Al-Ars, Z., Ahmed, N. & Bertels, K., 2018, IPC No. G06F, Priority date 9 Nov 2016, Priority No. WO 2018088896

    Research output: Patent

  82. Early Results from ERA¿Embedded Reconfigurable Architectures

    Wong, JSSM., Brandon, AAC., Anjam, F. & Seedorf, RAE., 2011, IEEE 9th International Conference on Industrial Informatics. Gomes, L. & Colombo, A. (eds.). Piscataway, NJ, USA: IEEE Society, p. 816-822 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Edge detection using Gabor coefficients through neural network

    Pourebrahimi, B., 2004, ASCI 2004 Proceedings of the tenth annual conference of the Advanced School for Computing and Imaging. van Wijk, JJ., Heijnsdijk, JWJ., Langendoen, KG. & Veltkamp, R. (eds.). Delft: Advanced School for Computing and Imaging, p. 19-27 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  84. Editorial Note on Memristor Models, Circuits and Architectures

    Sirakoulis, G. C. & Hamdioui, S., 2016, In : International Journal of Unconventional Computing. 12, 4, p. 247-250 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  85. Editorship:

    Vassiliadis, S. & ... [et Al], ., 2001, Euro-Par 2001: proceedings. Berlin: Springer, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. Effect of the degree of neighborhood on resource discovery in ad hoc grids

    Abdullah, MT., Bertels, K., Alima, LO. & Nawaz, Z., 2010, 23rd Intl. conf. ARCS 2010. Muller-Schloer, C., Karl, W. & Yehia, S. (eds.). Heidelberg: Springer, p. 174-186 13 p. (Lecture Notes in Computer Science; vol. 5974).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. Effective reverse conversion in residue number system processors

    Gbolagade, KA., 2010, Delft. 160 p.

    Research output: ThesisDissertation (TU Delft)

  88. Effects of bit line coupling on the faulty behavior of DRAMs

    Al-Ars, Z., Hamdioui, S. & van de Goor, AJ., 2004, Proceedings 22nd IEEE VLSI test symposium. Los Alamitos: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Effects of parametric constraints on the CRLB in gain and phase estimation problems

    Wijnholds, SJ. & van der Veen, AJ., 2006, In : IEEE Signal Processing Letters. 13, 10, p. 620-623 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  90. Efficent and highly portable deterministic multithreading (DetLock)

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2013, In : Computing. 95, p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Efficient Acceleration of the Pair-HMMs Forward Algorithm for GATK HaplotypeCaller on Graphics Processing Units

    Ren, S., Bertels, K. & Al-Ars, Z., 2018, In : Evolutionary Bioinformatics. 14, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  92. Efficient Methodology for ISO26262 Functional Safety Verification

    Silva, F. A. D., Bagbaba, A. C., Hamdioui, S. & Sauer, C., 1 Jul 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (eds.). Piscataway: IEEE, p. 255-256 2 p. 8854449

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. Efficient Runtime Management of Reconfigurable Hardware Resources

    Thomas, TM., 2011, Delft: Thomas Marconi. 150 p.

    Research output: ThesisDissertation (TU Delft)

  94. Efficient VLSI layouts of hypercubic networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 98-105 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  95. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2012, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 59, 2, p. 636-657 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  96. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2010, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 52, 3

    Research output: Contribution to journalArticleScientificpeer-review

  97. Efficient execution of video applications on heterogeneous multi- and many-core processors,

    Pereira de Azevedo Filho, AP., 2011, 160 p.

    Research output: ThesisDissertation (TU Delft)

  98. Efficient filtering with the co-vector processor

    Dang, BL., Engin, N. & Gaydadjiev, GN., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 351-356 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. Efficient hardware for antialiasing coverage mask generation

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, Proceedings Computer Graphics International. Werner, B. (ed.). Los Alamitos: IEEE, p. 257-265 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. Efficient hardware for tile-based rasterization

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 352-357 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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