601 - 700 out of 1,563Page size: 100
  1. Elastic Pipeline: Addressing GPU On-chip Shared Memory Bank Conflicts

    Gou, C. & Gaydadjiev, GN., 2011, Proceedings of the 8th ACM International Conference on Computing Frontiers. Prasanna, V. & Trancoso, P. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 1-11 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Electrical Modeling of STT-MRAM Defects

    Wu, L., Taouil, M., Rao, S., Marinissen, E. J. & Hamdioui, S., 2018, International Test Conference - Proceedings. Piscataway, NJ: IEEE, p. 1-10 10 p. 3.2

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Electron counting based high-radix multiplication in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2006, 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)O. s.n. (ed.). Piscataway-USA: IEEE Society, p. 4571-4574 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  5. Embedded Computer Systems: Architectures, Modeling, and Simulation

    Vassiliadis, S., Berekovic, M. & Hämäläinen, TD., 2007, Heidelberg: Springer. 463 p.

    Research output: Book/ReportBookProfessional

  6. Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints

    Nelson, AT., Molnos, AM., Beyranvand Nejad, A., Mirzoyan, D., Cotofana, SD. & Goossens, KGW., 2012, Workshop on embedded and cyber-physical systems education. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Embedded processor design using transport triggered architectures

    Corporaal, H., 2001, Proceedings. RHJM Otten (ed.). S.l.: IEEE Society, p. 25-34 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. Embedded processor design using transport triggered architectures

    Corporaal, H., 2000, SPECLOG'2000 proceedings. R Creutzburg & K Egiazarian (eds.). Monistamo, Finland: TTKK, p. 469-469

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. Embedded reconfigurable computing: the ERA approach

    Keramidas, G., Wong, JSSM., Anjam, F., Brandon, AAC., Seedorf, RAE., Scordino, C., Carro, L. & Matos, D., 2013, 11th IEEE International conference on industrial informatics. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Emerging crossbar-based hybrid nanoarchitectures for future computing systems

    Haron, NZB. & Hamdioui, S., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Emerging non-CMOS nanoelectronic devices-What are they?

    Haron, NZB., Hamdioui, S. & Cotofana, SD., 2009, The 4th annual IEEE international conference on nano/micro engineered and molecular systems. s.n. (ed.). Piscataway: IEEE Society, p. 63-68 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

    Hansson, A., Wiggers, M., Moonen, A., Goossens, KGW. & Bekooij, M., 2009, In : IET Computers and Digital Techniques. 3, 5, p. 398-412 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  13. Enabling vertical wormhole switching in 3D NoC-Bus hybrid systems

    Chen, C., Enachescu, M. & Cotofana, SD., 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ, USA: IEEE Society, p. 507-512 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

    Majzoub, S., Saleh, R. A., Ashraf, I., Taouil, M. & Hamdioui, S., 2019, In : IEEE Access. 7, p. 33115-33129 15 p., 8648367.

    Research output: Contribution to journalArticleScientificpeer-review

  15. Energy effective 3D stacked hybrid NEMFET-CMOS caches

    Lefter, M., Enachescu, M., Voicu, GR. & Cotofana, SD., 2014, Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures. Klein, JO. & Moritz, CA. (eds.). Piscataway, NJ, USA: IEEE Society, p. 151-156 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Energy efficient branch prediction on the cell SPE

    Briejer, M., Meenderinck, CH. & Juurlink, B., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 445-450 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Energy efficient wireless attitude determination system for spacecraft

    Gaydadjiev, GN., Amini, R. & Gill, EKA., 2012, Patent No. 2005664, Priority date 14 May 2012

    Research output: PatentOther research output

  18. Energy reduction techniques for caches and multiprocessors

    de Langen, PJ., 2009, Delft: s.n.. 140 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  19. Enhancing PUF based challenge-response sets by exploiting various background noise configurations

    Martin, H., Peris-Lopez, P., Di Natale, G., Taouil, M. & Hamdioui, S., 2019, In : Electronics (Switzerland). 8, 2, p. 1-14 14 p., 145.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Entropy decoding on TriMedia/CPU64

    Sima, M., Pol, E-J., van Eijndhoven, JTJ., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings Second international Samos workshop on Systems, Architectures, Modeling and Simulation. Leiden: SAMOS Initiative, p. 1-18 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  21. Erratum: Correction to: GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data (BMC bioinformatics (2019) 20 1 (520))

    Ahmed, N., Lévy, J., Ren, S., Mushtaq, H., Bertels, K. & Al-Ars, Z., 19 Nov 2019, In : BMC Bioinformatics. 20, 1, 1 p., 597.

    Research output: Contribution to journalComment/Letter to the editorScientificpeer-review

  22. Error Correction Code protected Data Processing Units

    Cucu Laurenciu, N., Gupta, T., Savin, V. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Evaluating Auto-adaptation Methods for Fine-grained Adaptable Processors

    Hoozemans, J., van Straten, J., Al-Ars, Z. & Wong, S., 2018, Architecture of Computing Systems : ARCS 2018; 31st International Conference on Architecture of Computing Systems. Berekovic, M., Buchty, R., Hamann, H., Koch, D. & Pionteck, T. (eds.). Cham: Springer, p. 255-268 14 p. (Lecture Notes in Computer Science, Also part of the Theoretical Computer Science and General Issues book sub series; vol. 10793).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Evaluating POWER Architecture for Distributed Training of Generative Adversarial Networks

    Hesam, A., Vallecorsa, S., Khattak, G. & Carminati, F., 2019, High Performance Computing - ISC High Performance 2019 International Workshops, Revised Selected Papers. Weiland, M., Juckeland, G., Alam, S. & Jagode, H. (eds.). Springer, p. 432-440 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 11887 LNCS).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. Evaluating various branch-prediction schemes for biomedical-implant processors

    Strydis, C. & Gaydadjiev, GN., 2009, 20th IEEE international conference on application-specific systems, architectures and processors. n.s. (ed.). Piscataway: IEEE Society, p. 169-176 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Evaluation framework for task scheduling algorithms in distributed reconfigurable systems

    Nadeem, MF., 2013, 141 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  27. Evaluation methodology for data communication-aware application partitioning

    Ashraf, I., Ostadzadeh, SA., Meeuws, RJ. & Bertels, KLM., 2013, 1st Workshop on Runtime and Operating Systems for the Many-core Era. Wolf, F., Mohr, B. & Dieter an Mey (eds.). Heidelberg: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Evaluation methodology for single electron encoded threshold logic gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2003, VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip. Glesner, M., Reis, R., Eveking, H., Mooney, V., Indrusiak, L. & Zipf, P. (eds.). Darmstadt, Germany: Technische Universität Darmstadt, p. 258-262 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Evaluation methodology for single electron encoded threshold logic gates

    Lageweg, CR. & Cotofana, SD., 2006, VLSI-SOC: From Systems to Chips. Glesner, M., Reis, R., Indrusiak, L., Mooney, V. & Eveking, H. (eds.). New York, USA: Springer, p. 263-280 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  30. Evaluation of SRAM faulty behavior under bit line coupling

    Al-Ars, Z. & Hamdioui, S., 2008, 3rd International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. 231-236 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Evaluation of a potential for automatic SIMD parallelization of embedded applications

    Manniesing, R., Karkowski, I. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 103-110 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Evaluation of different task scheduling policies in multi-core systems with recon¿gurable hardware

    Shahsavari, M., Al-Ars, Z. & Bertels, KLM., 2012, 8th International summer school on advanced computer architecture and compilation for high-performance and embedded systems. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Evaluation of military waveform processing on a COTS reconfigurable SDR processing platform

    Beheshti, B., Glossner, CJ., Routenberg, D. & Zannella, L., 2004, Proceedings of the 2004 Software Defined Radio Technical Conference. p. 147-151 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. Evaluation of parallel H.264 decoding strategies for the cell broadband engine

    Chi, C., Juurlink, B. & Meenderinck, CH., 2010, 2010 Intl. conference on supercomputing. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 105-114 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Evaluation of runtime task mapping heuristics with rSesame - a case study

    Sigdel, K., Thompson, M., Galuzzi, C., Pimentel, A. & Bertels, K., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 831-836 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2019, In : Journal of Electronic Testing: Theory and Applications (JETTA). 35, 3, p. 303-315 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  37. Experimental error mitigation via symmetry verification in a variational quantum eigensolver

    Sagastizabal, R., Bonet-Monroig, X., Singh, M., Rol, M. A., Bultink, C. C., Fu, X., Ostroukh, V. P., Muthusubramanian, N., Bruno, A., Beekman, M., Haider, N., O'Brien, T. E. & Dicarlo, L., 2019, In : Physical Review A. 100, 1, 6 p., 010302.

    Research output: Contribution to journalArticleScientificpeer-review

  38. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

    Sartor, A. L., Lorenzon, A. F., Carro, L., Kastensmidt, F., Wong, S. & Beck, A. C. S., 2017, In : ACM Journal on Emerging Technologies in Computing Systems. 13, 2, p. 13:1-13:21 21 p.

    Research output: Contribution to journalSpecial issueScientificpeer-review

  39. Exploiting Network-on-Chip Structural Redundancy for a Cooperative and Scalable Built-In Self-Test Architecture

    Strano, A., Gomez, C., Ludovici, D., Favalli, M., Gomez, ME. & Bertozzi, D., 2011, Proceedings Design, Automation and Test in Europe Conference and Exhibition (DATE 2011). Al-Hashimi, BM. & Rosenstiel, W. (eds.). Piscataway, NJ, USA: IEEE Society, p. 661-666 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. Exploiting SPMD Horizontal Locality

    Gou, C. & Gaydadjiev, GN., 2011, In : IEEE Computer Architecture Letters. 10, 1, p. 20-23 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Exploiting expendable process-margins in DRAMs for run-time performance optimization

    Chandrasekar, K., Goossens, S., Weis, C., Koedam, M., Akesson, B., Wehn, N. & Goossens, KGW., 2014, Proceedings of the 2014 International Conference on Design, Automation & Test in Europe. Fettweis, G. & Nebel, W. (eds.). Leuven, Belgium: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Exploiting parallelism of deblocking filter of H.264 on DTA architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 55-58 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Exploration of Alternative GPU Implementations of the Pair-HMMs Forward Algorithm

    Ren, S., Bertels, K. & Al-Ars, Z., 2016, Proceedings 3rd International Workshop on High Performance Computing on Bioinformatics. p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  44. Exploring ILP and TLP on a Polymorphic VLIW Processor

    Brandon, A., Hoozemans, J., van Straten, J. & Wong, S., 2017, Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. Knoop, J., Karl, W., Schulz, M., Inoue, K. & Pionteck, T. (eds.). Cham: Springer, p. 177-189 13 p. (Lecture Notes in Computer Science ; vol. 10172).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Exploring complex brain-simulation workloads on multi-GPU deployments

    Van Der Vlag, M. A., Smaragdos, G., Al-Ars, Z. & Strydis, C., 2019, In : ACM Transactions on Architecture and Code Optimization. 16, 4, 25 p., 53.

    Research output: Contribution to journalArticleScientificpeer-review

  46. Exploring test opportunities for memory and interconnects in 3D ICs

    Taouil, M., Lefter, M. & Hamdioui, S., 2012, International design & test symposium. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. Extending loop unrolling and shifting for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, Architecture and Compilers Embedded Systems symposium. s.n. (ed.). s.l.: s.n., p. 61-64 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Extending the cell SPE with energy efficient branch prediction

    Briejer, M., Meenderinck, CH. & Juurlink, BHH., 2010, 16th intl. Euro-Par conf.. D'Ambra, P., Guarracino, M. & Talia, D. (eds.). Berlijn: Springer, p. 304-315 12 p. (Lecture Notes in Computer Science; vol. 6271).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Extensions of the hArtes tool chain

    Meeuws, RJ., Ostadzadeh, SA., Nawaz, Z., Lu, Y., Thomas, TM., Sabeghi, M., Sima, VM. & Sigdel, K., 2012, Hardware/Software co-design for heterogeneous multi-core platforms. Bertels, KLM. (ed.). Berlin, Germany: Springer, p. 193-227 234 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  50. External memory controller for virtex II pro

    Donchev, B., Gaydadjiev, GN. & Kuzmanov, GK., 2006, 2006 International Symposium on System-on-Chip. s.n. (ed.). Piscataway: IEEE Society, p. 37-40 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. FLUX interconnection networks on demand

    Vassiliadis, S. & Sourdis, I., 2007, In : Journal of Systems Architecture. 53, 10, p. 777-793 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  52. FLUX networks: interconnects on demand

    Vassiliadis, S. & Sourdis, I., 2006, Proceedings 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Gaydadjiev, G., Glossner, J., Takala, J. & Vassiliadis, S. (eds.). Piscataway-USA: IEEE Society, p. 160-167 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. FPGA Implementation of Parallel Histogram Computation

    Shahbahrami, A., Hur, JY., Juurlink, B. & Wong, S., 2008, 2nd HIPEAC workshop on Reconfigurable Computing. s.n. (ed.). HiPEAC, p. 63-72 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. FPGA acceleration of the pair-HMMs forward algorithm for DNA sequence analysis

    Ren, S., Sima, V-M. & Al-Ars, Z., 2015, Proceedings - 2015 IEEE International Conference on Bioinformatics and Biomedicine. Huan, J. L., Miyano, S. & Shehu, A. (eds.). Danvers, MA: IEEE, p. 1465-1470 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. FPGA accelerator for real-time skin segmentation

    de Ruijsscher, B., Gaydadjiev, GN., Lichtenauer, JF. & Hendriks, EA., 2006, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia. Ha, S. & Chakraborty, S. (eds.). US: IEEE Society, p. 93-97 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. FPGA area allocation for parallel C applications

    Sima, VM., Panainte, E. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 369-374 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. FPGA implementation of low-frequency GPR signal algorithm using frequency stepped chirp signals in the time domain.

    Kyovtorov, VA., Kabakchiev, C., Behar, V., Kuzmanov, GK., Garvanov, I. & Doukovska, L., 2008, IEEE Intl. Radar Symposium 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. FPGA implementation of voice-over IP

    van den Braak, M. & Wong, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 338-342 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  59. FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges

    de Jong, M., Sima, VM., Bertels, KLM. & Thomas, D., 2015, Proceedings 2014 International Conference on Field Programmable Technologies. Kwok-Hay So, H. & Ma et al, Y. (eds.). Piscataway, NJ, USA: IEEE Society, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. FPGA-area allocation for partial run-time reconfiguration

    Moscu Panainte, E., Bertels, K. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 415-420 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  61. FPGA-based variable length decoders

    Nikara, J., Vassiliadis, S., Takala, J. & Liuha, P., 2003, IFIP VLSI-SoC 2003; IFIP WG 10.5 international conference on very large scale integration of system-on-chip. Glesner, M., Eveking, H., Indrusiak, LS., Reis, R., Mooney, V. & Zipf, P. (eds.). Darmstadt, Germany: Technische Universität Darmstadt, p. 437-441 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. FSM Non-minimal state encoding for low power

    Lemberski, I., Koegst, M., Cotofana, SD. & Juurlink, BHH., 2002, Proceedings 2002 23rd International conference on microelectronics, Vol. 2. Piscataway, NJ, USA: IEEE Society, p. 605-609 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Facilitating automatic test pattern generators using test point insertion

    Geuzebroek, MJ., van de Goor Ph D, AJ. & van Linden, JT., 2001, Global Semiconductor Manufacturing Technology. Business Briefing, p. 149-152

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  64. Fan-out enabled spin wave majority gate

    Mahmoud, A., Vanderveken, F., Adelmann, C., Ciubotaru, F., Hamdioui, S. & Cotofana, S., 2020, In : AIP Advances. 10, 3, p. 035119-1 - 035119-6 6 p., 035119.

    Research output: Contribution to journalArticleScientificpeer-review

  65. Fast and accurate workload-level neural network based IC energy consumption estimation

    Cucu Laurenciu, N. & Cotofana, S., 2017, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. IEEE, p. 1-4 4 p. 7981598

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Fast boolean logic mapped on memristor crossbar

    Xie, L., Du Nguyen, HA., Taouil, M., Hamdioui, S. & Bertels, K., 2015, Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD. Ozev, S. & Chung, SW. (eds.). Piscataway: IEEE Society, p. 335-342 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Fast smith-waterman hardware implementation

    Nawaz, Z., Bertels, KLM. & Sümbül, HE., 2010, IPDPS 2010 Conference 24th Intl. Parallel and Distributed processing symposium. s.n. (ed.). Piacataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Eighth Asian Test Symposium: proceedings. Los Alamitos: IEEE, p. 185-191 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Fault diagnosis using test primitives in random access memories

    Al-Ars, Z. & Hamdioui, S., 2009, 18th Asian test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 403-408 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. Fault tolerance architecture for reliable hybrid CMOS/nanodevices memory

    Haron, NZB. & Hamdioui, S., 2009.

    Research output: Contribution to conferencePosterProfessional

  71. Fault tolerance on multicore processors using deterministic multithreading

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, International design & test symposium. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. Fault tolerant structures for nanoscale gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2007, 2007 7th IEEE international conference on nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 605-610 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Fault-tolerant quantum error correction on near-term quantum processors using flag and bridge qubits

    Lao, L. & Almudever, C. G., 2020, In : Physical Review A. 101, 3, 11 p., 032333.

    Research output: Contribution to journalArticleScientificpeer-review

  74. Field programmable gate arrays with hardwired networks on chip

    Wahlah, MA., 2012, Delft. 229 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  75. Field-programmable custom computing machines - A taxonomy

    Sima, M., Vassiliadis, S., Cotofana, SD., van Eijndhoven, JTJ. & Vissers, K., 2002, Field-programmable logic and applications: Reconfigurable computing is going mainstream. Glesner, M., Zipf, P. & Renovell, M. (eds.). Berlin: Springer, p. 79-88 10 p. (Lecture Notes in Computer Science; vol. 2438).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Fine-and coarse-grain reconfigurable computing

    Vassiliadis, S. & Soudris, D., 2007, Heidleberg: Springer. 378 p.

    Research output: Book/ReportBookProfessional

  77. Fine-grain fault diagnosis for FPGA logic blocks

    Tzilis, S., Sourdis, I. & Gaydadjiev, GN., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 154-161 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. Fletcher: A framework to efficiently integrate FPGA accelerators with apache arrow

    Peltenburg, J., Van Straten, J., Wijtemans, L., Van Leeuwen, L., Al-Ars, Z. & Hofstee, P., 1 Sep 2019, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Sourdis, I., Bouganis, C-S., Alvarez, C., Toledo Diaz, L. A., Valero, P. & Martorell, X. (eds.). Institute of Electrical and Electronics Engineers (IEEE), p. 270-277 8 p. 8892145

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Flexible pipelining design for recursive variable expansion

    Nawaz, Z., Thomas, TM., Stefanov, TP. & Bertels, K., 2009, 23rd IEEE international parallel & distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units

    Nguyen-Ly, T. T., Gupta, T., Pezzin, M., Savin, V., Declercq, D. & Cotofana, S., 2016, Proceedings - 19th Euromicro Conference on Digital System Design (DSD 2016). Kitsos, P. (ed.). Piscataway: IEEE, p. 230-237 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Floating point to fixed point conversion of C code

    Cilio, AGM. & Corporaal, H., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 229-243 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. Floating-point matrix multiplication in a polymorphic processor

    Kuzmanov, GK. & Oijen van, WM., 2007, ICFPT 2007. Takeshi Ikenaga Hideharu Amano, A. Y. (ed.). s.l., p. 249-252 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Flux caches: what are they and are they useful?

    Gaydadjiev, GN. & Vassiliadis, S., 2005, Proceedings of the 5th international workshop on computer systems: architectures, modelling, and simulation (SAMOS 2005). Hämäläinen, TD., Pimentel, AD., Takala, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 92-103 12 p. (Lecture Notes in Computer Science; vol. 3553).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications

    Hoozemans, J., de Jong, R., van der Vlugt, S., Van Straten, J., Elango, U. K. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 47-59 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  85. Framework for fault analysis and test generation in drams

    Al-Ars, Z., Hamdioui, S., Mueller, G. & van de Goor, AJ., 2005, Proceedings of design, automation and test in Europe 2005 (DATE 05). s.n. (ed.). Piscataway: IEEE Society, p. 100-105 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems

    Borodin, D., Siauw, WG. & Cotofana, SD., 2011, Proceedings International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Carro, L. & Pimentel, A. (eds.). Piscataway, NJ, USA: IEEE Society, p. 311-317 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. Future challenges in memory testing

    Hamdioui, S. & Gaydadjiev, GN., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 78-83 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. Future directions of (programmable and reconfigurable) embedded processors

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, SAMOS 2002 Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation. Leiden: SAMOS Initiative, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  89. Future directions of programmable and reconfigurable embedded processors

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2004, Domain-specific processors; Systems, architectures, modeling, and simulation. Bhattacharyya, SS., Deprettere, EF. & Teich, J. (eds.). New York: Marcel Dekker, p. 235-258 24 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  90. Future wireless convergence platforms

    Glossner, CJ., Moudgill, M., Iancu, D., Nacer, G., Jintukar, S., Stanley, S., Samori, M., Raja, T., Schulte, M. & Vassiliadis, S., 2005, Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis. Eles, P., Jantsch, A. & Bergamaschi, RA. (eds.). New York, USA: Association for Computing Machinery (ACM), p. 7-12 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data

    Ahmed, N., Lévy, J., Ren, S., Mushtaq, H., Bertels, K. & Al-Ars, Z., 25 Oct 2019, In : BMC Bioinformatics. 20, 1, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  92. GPU Accelerated API for Alignment of Genomics Sequencing Data

    Ahmed, N., Mushtaq, H., Bertels, K. & Al-Ars, Z., Nov 2017, 2017 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Hu, X., Shyu, C. R., Bromberg, Y., Gao, J., Gong, Y., Korkin, D., Yoo, I. & Zheng, J. H. (eds.). Danvers: IEEE, p. 510-515 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. GPU Accelerated Sequence Alignment with Trace-back for GATK HaplotypeCaller

    Ren, S., Ahmed, N., Bertels, K. & Al-Ars, Z., 2019, In : BMC Genomics. 20, p. 103-116 184.

    Research output: Contribution to journalArticleScientificpeer-review

  94. GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, Proceedings - 29th International Conference on Architecture of Computing Systems, ARCS 2016. Hannig, F., Cardoso, J. M. P., Pionteck, T., Fey, D., Schröder-Preikschat, W. & Teich, J. (eds.). Springer, p. 130-142 13 p. (Lecture Notes in Computer Science; vol. 9637).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization

    Ren, S., Bertels, K. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 497-502 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. GPU-Accelerated Protein Sequence Alignment

    Hasan, L., Kentie, M. & Al-Ars, Z., 2011, 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). Khoo, M., Cauwenberghs, G. & Weiland, J. (eds.). Piscataway, NJ, USA: IEEE Society, p. 2442-2446 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. GPU-based stochastic-gradient optimization for non-rigid medical image registration in time-critical applications

    Bhosale, P., Staring, M., Al-Ars, Z. & Berendsen, F. F., 2018, Medical Imaging 2018: Image Processing. Angelini, E. D. & Landman, B. A. (eds.). Bellingham, WA: SPIE, p. 1-8 105740R. (Proceedings of SPIE; vol. 10574).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. GRAAL - A development framework for embedded graphics accelerators

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, Design, automation and test in Europe; Date04 Proceedings. Gielen, G. & Figueras, J. (eds.). Piscataway: IEEE Society, p. 1366-1367 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  99. GRAAL: a framework for low-power 3D graphics accelerators

    Juurlink, B., Crisu, D., Antochi, I., Cotofana, SD. & Vassiliadis, S., 2008, In : IEEE Computer Graphics and Applications. 28, 4, p. 63-73 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  100. GSM/GPRS physical layer on sandblaster DSP

    Kalavai, R., Senthilvelan, M., Agrawal, S., Jinturkar, S. & Glossner, CJ., 2006, 2006 Software Defined Radio Technical Conference and Product Exposition. s.n. (ed.). USA: s.l., p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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