701 - 800 out of 1,593Page size: 100
  1. Framework for fault analysis and test generation in drams

    Al-Ars, Z., Hamdioui, S., Mueller, G. & van de Goor, AJ., 2005, Proceedings of design, automation and test in Europe 2005 (DATE 05). s.n. (ed.). Piscataway: IEEE Society, p. 100-105 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems

    Borodin, D., Siauw, WG. & Cotofana, SD., 2011, Proceedings International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Carro, L. & Pimentel, A. (eds.). Piscataway, NJ, USA: IEEE Society, p. 311-317 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Future challenges in memory testing

    Hamdioui, S. & Gaydadjiev, GN., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 78-83 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Future directions of (programmable and reconfigurable) embedded processors

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, SAMOS 2002 Proceedings of the Second International Samos Workshop on Systems, Architectures, Modeling, and Simulation. Leiden: SAMOS Initiative, p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  5. Future directions of programmable and reconfigurable embedded processors

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2004, Domain-specific processors; Systems, architectures, modeling, and simulation. Bhattacharyya, SS., Deprettere, EF. & Teich, J. (eds.). New York: Marcel Dekker, p. 235-258 24 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  6. Future wireless convergence platforms

    Glossner, CJ., Moudgill, M., Iancu, D., Nacer, G., Jintukar, S., Stanley, S., Samori, M., Raja, T., Schulte, M. & Vassiliadis, S., 2005, Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis. Eles, P., Jantsch, A. & Bergamaschi, RA. (eds.). New York, USA: Association for Computing Machinery (ACM), p. 7-12 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data

    Ahmed, N., Lévy, J., Ren, S., Mushtaq, H., Bertels, K. & Al-Ars, Z., 25 Oct 2019, In : BMC Bioinformatics. 20, 1, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. GPU Accelerated API for Alignment of Genomics Sequencing Data

    Ahmed, N., Mushtaq, H., Bertels, K. & Al-Ars, Z., Nov 2017, 2017 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Hu, X., Shyu, C. R., Bromberg, Y., Gao, J., Gong, Y., Korkin, D., Yoo, I. & Zheng, J. H. (eds.). Danvers: IEEE, p. 510-515 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. GPU Accelerated Sequence Alignment with Trace-back for GATK HaplotypeCaller

    Ren, S., Ahmed, N., Bertels, K. & Al-Ars, Z., 2019, In : BMC Genomics. 20, p. 103-116 184.

    Research output: Contribution to journalArticleScientificpeer-review

  10. GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, Proceedings - 29th International Conference on Architecture of Computing Systems, ARCS 2016. Hannig, F., Cardoso, J. M. P., Pionteck, T., Fey, D., Schröder-Preikschat, W. & Teich, J. (eds.). Springer, p. 130-142 13 p. (Lecture Notes in Computer Science; vol. 9637).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization

    Ren, S., Bertels, K. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 497-502 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. GPU-Accelerated Protein Sequence Alignment

    Hasan, L., Kentie, M. & Al-Ars, Z., 2011, 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). Khoo, M., Cauwenberghs, G. & Weiland, J. (eds.). Piscataway, NJ, USA: IEEE Society, p. 2442-2446 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. GPU-based stochastic-gradient optimization for non-rigid medical image registration in time-critical applications

    Bhosale, P., Staring, M., Al-Ars, Z. & Berendsen, F. F., 2018, Medical Imaging 2018: Image Processing. Angelini, E. D. & Landman, B. A. (eds.). Bellingham, WA: SPIE, p. 1-8 105740R. (Proceedings of SPIE; vol. 10574).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. GRAAL - A development framework for embedded graphics accelerators

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, Design, automation and test in Europe; Date04 Proceedings. Gielen, G. & Figueras, J. (eds.). Piscataway: IEEE Society, p. 1366-1367 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. GRAAL: a framework for low-power 3D graphics accelerators

    Juurlink, B., Crisu, D., Antochi, I., Cotofana, SD. & Vassiliadis, S., 2008, In : IEEE Computer Graphics and Applications. 28, 4, p. 63-73 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. GSM/GPRS physical layer on sandblaster DSP

    Kalavai, R., Senthilvelan, M., Agrawal, S., Jinturkar, S. & Glossner, CJ., 2006, 2006 Software Defined Radio Technical Conference and Product Exposition. s.n. (ed.). USA: s.l., p. -

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Gaps and requirements for automatic generation of space layouts with optimised energy performance

    Du, T., Turrin, M., Jansen, S., van den Dobbelsteen, A. & Fang, J., 2020, In : Automation in Construction. 116, 18 p., 103132.

    Research output: Contribution to journalReview articleScientificpeer-review

  18. Garbage collection for the Delft Java Processor

    Berlea, A., Cotofana, SD., Athanasiu, I., Glossner, CJ. & Vassiliadis, S., 2000, Proceedings. MH Hamza (ed.). Annaheim: iASTED, p. 232-238 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. General purpose computing with reconfigurable acceleration

    Brandon, AAC., Sourdis, I. & Gaydadjiev, GN., 2010, 2010 intl. conf on field programmable logic and applications. s.n. (ed.). Piscataway: IEEE Society, p. 588-591 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. General-purpose Huffman encoding extension

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ITCC 2000. Los Alamitos: IEEE, p. 158-163 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  21. Generalized matrix method for efficient residue to decimal conversion

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Asia pacific conference on circuits ans systems. s.n. (ed.). Piscataway: IEEE Society, p. 1414-1417 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Generic loop parallelization for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 35-39 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Global program optimization: register allocation of static scalar objects

    Cilio, AGM. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 52-57 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Global variable promotion: using registers to reduce cache power dissipation

    Cilio, AGM. & Corporaal, H., 2002, Compiler construction: 11th International conference; proceedings / CC 2002. Horspool, RN. (ed.). Berlin: Springer, p. 247-261 15 p. (Lecture Notes in Computer Science; vol. 2304).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. GraalBench: a 3D graphics benchmark suite for mobile phones

    Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2004, Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on languages, compilers, and tools for embedded systems (LCTES'04). New York: Association for Computing Machinery (ACM), p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. Graph covering for generating instruction specific application instructions: an overview of some existing methods

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 502-507 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. Graph theory and application specific processors

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 23-29 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  28. Graphene Nanoribbon Based Complementary Logic Gates and Circuits

    Jiang, Y., Cucu Laurenciu, N., Wang, H. & Cotofana, S. D., 2019, In : IEEE Transactions on Nanotechnology. 18, p. 287-298 12 p., 8666174.

    Research output: Contribution to journalArticleScientificpeer-review

  29. Growing on the inside: soulful characters for video games

    Bidarra, AR., Schaap, R. & Goossens, KGW., 2010, Proceedings of IEEE Conference on Computational Intelligence and Games. s.n. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 337-344 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Guest Editorial Memristive-Device-Based Computing

    Hamdioui, S., Gaillardon, P. E., Fey, D. & Simunic Rosing, T., 2018, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 12, p. 2581-2583 3 p., 8554356.

    Research output: Contribution to journalEditorialScientific

  31. H.264/AVC HDTV motion compensation soft IP

    Pereira de Azevedo Filho, AP., Agostini, L., Susin, A. & Bampi, S., 2007, IP07 proceedings. s.m. (ed.). Wordpress.com, p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. HArtes: hardware-software codesign for heterogeneous multicore platforms

    Bertels, KLM., Sima, VM., Yankova, YD. & Kuzmanov, GK., 2010, In : IEEE Micro. 30, 5, p. 88-97 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. HIPEAC: upcoming challenges in reconfigurable computing

    Sourdis, I. & Gaydadjiev, GN., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 35-52 293 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  34. HLL-to-HDL generation: results and challenges

    Yankova, YD., Bertels, KLM., Vassiliadis, S., Kuzmanov, GK. & Chaves Fernandes, R., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 356-364 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. HMMER Performance Model for Multicore Architectures

    Isaza Ramirez, S., Houtgast, E. & Gaydadjiev, GN., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 257-261 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. HaRTES toolchain early evaluation: profiling, compilation and HDL generation

    Bertels, K., Kuzmanov, GK., Panainte, E., Gaydadjiev, GN., Yankova, YD., Sima, VM., Sigdel, K., Meeuws, RJ. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 402-408 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Haar-based interconnect coding for energy effective medium/long range data transport

    Cucu Laurenciu, N. & Cotofana, S., 2017, Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. Alioto, M., Li, H., Becker, J., Schlichtmann, U. & Sridhar, R. (eds.). Piscataway, NJ: IEEE, p. 375-380 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Hacking and protecting IC hardware

    Hamdioui, S., di Natale, G., van Battum, G., Danger, J-L., Smailbegovic, F. & Tehranipoor, M., 2014, Proceedings of the 2014 International Conference on Design, Automation & Test in Europe. Nebel, W. & Fettweis, G. (eds.). Leuven, Belgium: EDAA, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. Hand segmentation by fusing 2D and 3D data

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2010, Intl conf. on Computer modeling and simulation. s.n. (ed.). Los Alamitos, CA: IEEE Society, p. 99-103 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. HandBench: a benchmarking suite for processors embedded in handheld devices

    de Langen, P., Juurlink, BHH. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 57-62 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  41. Hardware Acceleration of Bioinformatics Sequence Alignment Applications,

    Hasan, L., 2011, 130 p.

    Research output: ThesisDissertation (TU Delft)

  42. Hardware OS Communication Service and Dynamic Memory Management for RSoCs

    Narayanan, S., Chillet, D., Pillement, S. & Sourdis, I., 2011, International Conference on ReConFigurable Computing and FPGAs. Athanas, P., Becker, J. & Cumplido, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths

    Houtgast, E. J., Sima, V-M., Bertels, K. & Al-Ars, Z., 2018, In : Computational Biology and Chemistry. 75, p. 54-64 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  44. Hardware acceleration of sequence alignment algorithms: an overview

    Hasan, L., Al-Ars, Z. & Vassiliadis, S., 2007, Design & Technology of Integrated Systems 2007. Hamdiuoi, S., O. A. (ed.). Piscataway: IEEE Society, p. 96-101 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. Hardware acceleration of the SRP authentication protocol

    Groen, P., Hämäläinen, P., Juurlink, BHH. & Hämäläinen, T., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 70-77 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Hardware algorithms for tile-based real-time rendering

    Crisu, D., 2012, Delft. 208 p.

    Research output: ThesisDissertation (TU Delft)

  47. Hardware and a tool chain for ADRES

    de Sutter, B., Mei, B., Bartic, A., Vander Aa, T., Berekovic, M., Mignolet, J-Y., Croes, K., Coene, P., Cupac, M., Couvreur, A., Folens, A., Dupont, S., van Thielen, B., Kanstein, A., Kim, H-S. & Kim, S., 2006, Reconfigurable Computing: Architectures and Applications. Bertels, K., Cardoso, J. & Vassiliadis, S. (eds.). Heidelberg: Springer, p. 425-430 6 p. (Lecture Notes in Computer Science; vol. 3985).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z., Nawaz, Z. & Bertels, K., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 135-140 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. Hardware-based aging mitigation scheme for memory address decoder

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 2019, 2019 IEEE European Test Symposium (ETS). IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. Hardwired MPEG-4 repetitive padding

    Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2005, In : IEEE Transactions on Multimedia. 7, 2, p. 261-268 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  51. Hardwired NOC infrastructure with integrated configuration and functional architectures

    Wahlah, MA. & Goossens, KGW., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 122-125 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. Hardwired Paeth codec for portable network graphics (PNG)

    Hakkennes, EA. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 318-325 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. Hardwired networks on chip in FPGAs to unify functional and configuration interconnects

    Goossens, KGW., Bennebroek, M., Hur, JY. & Wahlah, MA., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: IEEE Society, p. 45-54 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. Hashed addressed caches for embedded pointer based codes

    Stanca, VM., Vassiliadis, S., Cotofana, SD. & Corporaal, H., 2000, In: A Bode, ...(et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 956-968 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  55. Hashing for IDS pattern matching

    Sourdis, I. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 66-68 3 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Hashing functions performance in packet classification

    Ahmadi, M. & Wong, S., 2007, Proceeding of the 2nd International conference on the latest advances in networks. s.n. (ed.). s.l., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. Heterogeneous hardware accelerator architecture for streaming image processing

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2013, International Conference on Advanced Technologies for Communications. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. Heterogeneous hardware accelerators interconnect: an overview

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2013, NASA/ESA Conference on adaptive hardware and systems. s.n. (ed.). Piscataway: IEEE Society, p. 189-195 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. Heterogeneous hardware accelerators interconnect: an overview

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-12 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. Heterogeneous hardware/software acceleration of the BWA-MEM DNA alignment algorithm

    Ahmed, N., Sima, VM., Houtgast, E., Bertels, K. & Al-Ars, Z., 7 Jan 2016, Proceedings of the 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD. Marculescu, D. & Lim, F. (eds.). Piscataway, NJ, USA: IEEE Society, p. 240-246 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. Heterogeneous trading agents

    Neuberg, L. & Bertels, KLM., 2003, In : Complexity. 8, 5, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientific

  62. Heuristic algorithms for primitive traversal acceleration in tile-based rasterization

    Huang, L., Crisu, D. & Cotofana, SD., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 408-414 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  63. Hierarchical SNR scalable video coding with adaptive quantization for reduced drift error

    Choupani, R., Wong, S. & Tolun, M., 2015, Proceedings - 10th International Conference on Computer Vision Theory and Applications. Imai, F., Braz, J. & Battiato, S. (eds.). Lisbon, Portugal: SciTePress, p. 117-123 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. Hierarchical approach for hardware/software systems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 2000, CAS 2000 proceedings. Vol. 1. 2000 international semicondutor conference 23rd edition. D Dascalu (ed.). Piscataway: IEEE Society, p. 223-226 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Hierarchical intelligent mixed simulation

    Niculiu, T. & Cotofana, SD., 2002, Modelling and simulation 2002; 16th European simulation multiconference. Amborski, K. & Meuth, H. (eds.). Ghent: SCS Publishing House, p. 159-162 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  66. Hierarchical intelligent simulation

    Niculiu, T. & Cotofana, SD., 2004, Cognitive, emotive and ethical aspects of decision making in humans and in artificial intelligence. Smit, I., Wallach, W. & Lasker, GE. (eds.). Ontario: Int'l Inst. for Adv. Studies in Systems Res. and Cybernetics, p. 45-50 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Hierarchical intelligent simulation

    Niculiu, T. & Cotofana, SD., 2001, ESM'2001: proceedings. San Diego: Society for Computer Simulation International, p. 243-246 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  68. Hierarchical interfaces for hardware/software systems

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2000, 14th European simulation multiconference. D Landeghem, V. (ed.). San Diego: Society for Computer Simulation International, p. 647-654 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Hierarchical mixed simulation for intelligent interfaces of microsystems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 1999, CAS '99 proceedings. Vol. 2. S.l.: IEEE Society, p. 515-518 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. Hierarchical models for intelligent reconfigurable simulation

    Niculiu, T., Ciuc, M. & Cotofana, SD., 2004, Proceedings of the Fifteenth IASTED International Conference on Modelling and Simulation. Anaheim: ACTA Press, p. 350-355 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. Hierarchical simulated reconfigurable intelligence templates

    Niculiu, T. & Cotofana, SD., 2003, Proceedings of the IASTED international conference on intelligent systems and control. Hamza, MH. (ed.). Anaheim: ACTA Press, p. 39-44 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. Hierarchical templates for simulated intelligence

    Niculiu, T. & Cotofana, SD., 2004, In : EUROSIM- Simulation News Europe. 38/39, p. 16-22 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  73. Hierarchical testability assisted intelligent simulation

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2004, In : International Journal of Modelling & Simulation. 24, 1, p. 26-36 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. High Level Quantitative Hardware Prediction Modeling using Statistical methods

    Meeuws, RJ., Galuzzi, C. & Bertels, KLM., 2011, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Carro, L. & Pimentel, A. (eds.). Piscataway: IEEE Society, p. 140-149 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL

    Houtgast, E., Sima, V. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 492-496 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. High level quantitative interconnect estimation for early design space exploration

    Meeuws, RJ., Sigdel, K., Yankova, YD. & Bertels, K., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 317-320 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. High performance and resource efficient biological sequence alignment

    Hasan, L., Al-Ars, Z. & Taouil, M., 2010, IEEE EMB. s.n. (ed.). s.n., p. 1767-1770 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. High quality simulation tool for memory redundancy algorithms

    Yamasaki, K., Hamdioui, S., Al-Ars, Z., van Genderen, AJ. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 133-138 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. High radix addition via conditional charge transport in single electron tunneling technology

    Meenderinck, CH., Cotofana, SD. & Lageweg, CR., 2005, Proceedings of the 16th IEEE International conference on Application-Specific Systems Architectures and Processors (ASAP). Vassiliadis, S., Dimopoulos, N. & Rajopadhye, S. (eds.). Los Alamitos: IEEE Society, p. 294-302 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. High speed merged-datapath design for run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A., Shahbahrami, A. & Gaydadjiev, GN., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 339-343 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. High speed reconfigurable computation for electronic instrumetation in space applications

    Lampridis, D., Cotofana, SD. & Kraft, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 221-227 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. High-bandwidth address generation unit

    Calderon, H., Galuzzi, C., Gaydadjiev, GN. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 251-262 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. High-bandwidth address generation unit

    Galuzzi, C., Gou, C., Calderon, H., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  84. High-level energy estimation for ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2003, Third international workshop on systems, architectures, modeling, and simulation. s.n. (ed.). Leiden: SAMOS Initiative, p. 148-153 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  85. High-level energy estimation for ARM-based SOCs

    Crisu, D., Cotofana, SD., Vassiliadis, S. & Liuha, P., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 168-177 10 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. High-level intelligence-oriented simulation

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2002, CAS 2002 proceedings, Volume 2. Piscataway, NJ, USA: IEEE Society, p. 381-385 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. High-level power estimation and optimization of DRAMs

    Chandrasekar, K., 2014, 144 p.

    Research output: ThesisDissertation (TU Delft)

  88. High-level synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

    Nane, R., Sima, VM., Pham Quoc Cuong, P., Goncalves, F. & Bertels, K., 2014, Proceedings - 12th IEEE International Conference on Embedded and Ubiquitous Computing. Santambrogio, MD. (ed.). Los Alamitos, CA, USA: IEEE, p. 138-145 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. High-performance cluster-fault tolerance scheme for hybrid nanoelectronic memories

    Haron, NZB. & Hamdioui, S., 2010, 2010 IEEEIntl. symp. on defect and fault tolerance in VLSI systems. s.n. (ed.). Piscataway: IEEE Society, p. 144-151 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. High-performance processing in networked and grid environments

    Ahmadi, M., 2010, Delft. 131 p.

    Research output: ThesisDissertation (TU Delft)

  91. High-performance switching based on buffered crossbar fabrics

    Mhamdi, L., Hamdi, M., Kachris, C., Wong, S. & Vassiliadis, S., 2006, In : Computer Networks. 50, p. 2271-2285 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  92. High-performance, Cost-effective 3D Stacked Wide-Operand Adders

    Voicu, G. R. & Cotofana, S. D., 4 Aug 2016, In : IEEE Transactions on Emerging Topics in Computing. 5, 2, p. 179-192 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  93. High-radix addition and mulltiplication in the electron counting paradigm using single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2006, Embedded Computer Systems: Architectures, Modeling, and Simulation. Vassiliadis, S., Wong, S. & Hamalainen, TD. (eds.). Heidelberg: Springer, p. 447-456 10 p. (Lecture Notes in Computer Science; vol. 4017).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. High-speed hybrid threshold-Boolean logic

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 384-388 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  95. High-speed hybrid threshold-boolean logic counters and compressors

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, MWSCAS-2002; proceedings of the 2002 45th Midwest symposium on circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 457-460 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. How significant will be the test cost share for 3D Die-to-Wafer stacked-ICs?

    Taouil, M., Hamdioui, S. & Marinissen, E., 2011, 6th International conference on Design & Technology of Integrated Systems in nanoscale era. Voyiatzis, I. & Wunderlich, H-J. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Hybrid NEMS-CMOS Architectures for Ultra Low Power Smart Systems: Architectures for Ultra Low Power Smart Systems

    Enachescu, M., 12 Apr 2016, 155 p.

    Research output: ThesisDissertation (TU Delft)

  98. Hybrid interconnect design for heterogeneous hardware accelerators

    Pham Quoc Cuong, P., Heisswolf, J., Wenner, S., Al-Ars, Z., Becker, JA. & Bertels, KLM., 2013, Design, automation & test in Europe conference & exhibition. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. Hybrid resource discovery mechanism in ad hoc grid using structured overlay

    Abdullah, MT., Onana Alima, L., Sokolov, S., Calomme, D. & Bertels, K., 2009, In : Lecture Notes in Computer Science. 5455, p. 108-119 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  100. IEEE-Compliant IDCT on FPGA-augmented trimedia

    Sima, M., Cotofana, SD., van Eijndhoven, JTJ., Vassiliadis, S. & Vissers, K., 2005, In : Journal of V LSISignal Processing. 39, 3, p. 195-212 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

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