1. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A comparison between processor architectures for multimedia applications

    Shahbahrami, A., Juurlink, BHH. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 1-15 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  5. A comparison of two SIMD implementations of the 2D discrete wavelet transform

    Shahbahrami, A. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 169-177 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A composable, energy-managed, realtimeMPSOC platform

    Goossens, KGW., Molnos, AM., Ambrose, JA., Nelson, AT., Stefan, RA. & Cotofana, SD., 2010, 12th Intl. optimization electrical and electronic equipment. s.n. (ed.). s.l.: IEEE Society, p. 870-876 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A control microarchitecture for fault-tolerant quantum computing

    Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

    Medeiros, G. C., Bolzani Poehls, L. M., Taouil, M., Luis Vargas, F. & Hamdioui, S., 2018, In : Microelectronics Reliability. 88-90, p. 355-359 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

    Cucu Laurenciu, N. & Cotofana, SD., 2013, 21st IFIP/IEEE international conference on very large scale integration. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A drift-reduced hierarchical wavelet coding scheme for scalable video transmissions

    Choupani, R., Wong, S. & Tolun, MR., 2009, The first international conference on advances in multimedia. Burdescu, DD., Crespi, N. & Dini, O. (eds.). Piscataway: IEEE Society, p. 68-73 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. A dynamic pricing and bidding strategy for autonomous agents in grids

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2007, 6th international joint conference on autonomous agents and multi-agent systems. Joseph S Bergamaschi S, D. Z. (ed.). s.l.: s.l., p. 70-81 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. A dynamically reconfigurable queue scheduler

    Kachris, C. & Vassiliadis, S., 2006, 2006 International conference on Field Programmable Logic and Applications. Koch, A., Leong, P. & Boemo, E. (eds.). Piscataway: IEEE Society, p. 869-872 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. A family of single electron static buffered Boolean logic

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 339-343 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  14. A fast CRC update implementation

    Lu, W. & Wong, JSSM., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 113-120 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. A fault primitive based analysis of dynamic memory faults

    Hamdioui, S., Gaydadjiev, GN. & van de Goor, AJ., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 84-89 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A fault primitive based analysis of linked faults in RAMs

    Al-Ars, Z., Hamdioui, S. & van de Goor, AJ., 2003, MTDT 2003; Records of the 2003 international workshop on memory technology, design and testing. s.n. (ed.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. A flexible simulator for exploring hardware rasterizers

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. A flexible simulator of pipelined processors

    Juurlink, BHH., Bertels, KLM. & Li, B., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 483-493 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A framework for adaptive matchmaking in distributed computing

    Sigdel, K., Bertels, K., Pourebrahimi, B., Vassiliadis, S. & Shuai, Y., 2005, Proceedings of GRID workshop Cracow-04. Bubak, M., Turala, M. & Wiatr, K. (eds.). Kraków: Cyfronet AGH, p. 150-157 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A full adder implementation using SET based linear threshold gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. Baric, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 665-669 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of a multi-level reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013.

    Research output: Contribution to conferencePosterScientific

  24. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of total reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A generic digital architecture & compiler for implantable devices

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 69-72 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. A hardware cache memcpy accelerator

    Wong, JSSM., Campos Soares Borrego, F. & Vassiliadis, S., 2006, International Conference on Field Programmable Technology. s.n. (ed.). Piscataway: IEEE Society, p. 141-147 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. A hardware implementation of the unisim pipeline model

    Stefan, RA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 259-263 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. A hardware/software co-simulation environment for graphics accelerator development in ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 255-267 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  29. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2012, Conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. A hierarchical sparse matrix storage format for vector processors

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2003, IPDPS 2003; 17th international parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. A high-level debug environment for communication-centric debug

    Goossens, KGW., Vermeulen, B. & Beyranvand Nejad, A., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 202-207 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

    Nadeem, M., Wong, S., Kuzmanov, GK. & Shabbir, A., 2009, 2009 IEEE/ACM/IFIP 7th workshop on embedded for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 18-27 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. A hybrid cross layer architecture for wireless protocol stacks

    Chang, Z. & Gaydadjiev, GN., 2008, 2008 international wireless communications and mobile computing conference. s.n. (ed.). Piscataway: IEEE Society, p. 279-285 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  36. A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

    Strano, A., Ludovici, D. & Bertozzi, D., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 20-27 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  38. A lightweight speculative and predicative scheme for hardware execution

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 130-141 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  41. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 283-293 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  43. A linear threshold gate implemantation in single electron technology

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. A Jacobs (ed.). Los Alamitos: IEEE, p. 93-98 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. A load/store unit for a memcpy hardware accelerator

    Vassiliadis, S., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 537-541 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  47. A low cost method to tolerate soft errors in the NoC router control plane

    Chen, C. & Cotofana, SD., 2013, 26th Annual IEEE International SoC Conference). s.n. (ed.). Piscataway: IEEE Society, p. 374-379 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. A low power 2D/3D graphics accelerator: The initial design

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2001, S.l.: s.n. 18 p.

    Research output: Book/ReportReportProfessional

  49. A low power 2D/3D graphics accelerator; A preliminary ISA

    Antochi, I., Juurlink, BHH. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 40 p.

    Research output: Book/ReportReportProfessional

  50. A low-cost BRAM-Based function reuse for configurable soft-core processors in FPGAs

    Becker, P. H. E., Sartor, A. L., Brandalero, M., Trevisan Jost, T., Wong, S., Carro, L. & Beck, A. C., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer, p. 499-510 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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