1. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. A low-cost, power-efficient texture cache architecture

    Antochi, I., Juurlink, BHH. & Cilio, AGM., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 250-257 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. A low-power carry skip adder with fast saturation

    Schulte, MJ., Chirca, K., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 269-279 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. A low-power multithreaded processor for baseband communication systems

    Schulte, M., Glossner, CJ., Mamidi, S., Moudgill, M. & Vassiliadis, S., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 393-402 10 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A low-power threshold logic family

    Padure, MD., Cotofana, SD., Vassiliadis, S., Dan, C. & Bodea, M., 2002, ICECS 2002; 9th IEEE International Conference on Electronica, Circuits and Systems. Piscatawy, NJ. USA: IEEE Society, p. 657-660 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A mathematical game and its applications to the design of interconnection networks

    Yeh, CH. & Varvarigos, EA., 2001, Proceedings. Los Alamitos: IEEE, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A matrix-multiply unit for posits in reconfigurable logic leveraging (Open)CAPI

    Chen, J., Al-Ars, Z. & Hofstee, H. P., 2018, Proceedings of the Conference for Next Generation Arithmetic, CoNGA 2018. Association for Computing Machinery (ACM), p. 1-5 5 p. 1

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. A memcpy hardware accelarator solution for non cache-line aligned copies

    Campos Soares Borrego, F. & Wong, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 397-402 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. A memory-optimized bloom filter using an additional hashing function

    Ahmadi, M. & Wong, S., 2008, IEEE GLOBECOM 2008. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. A method and system for power management

    Molnos, AM. & Goossens, KGW., 2013, Patent No. US 8569911 B2, Priority date 29 Oct 2013

    Research output: Patent

  12. A method and system for power management

    Molnos, AM. & Goossens, KGW., 2009, Patent No. WO 2009125371 A2, Priority date 15 Oct 2009

    Research output: Patent

  13. A method to analyze the fault tolerance of molecular quantum-dot cellular automata systems

    Milosavljevic, D. & Cotofana, SD., 2006, Proceedings 2006 International Semiconductor conference. s.n. (ed.). Piscataway: IEEE Society, p. 399-402 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. A minimalistic for reconfigurable WFS-based immersive-audio

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, 2010 Intl. conf. on reconfigurable computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. A modified merging approach for datapath configuration time reduction

    Fazlali, M., 2010, Reconfigurable computing: architectures, tools and applications. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 318-328 11 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2006, Proc. Euromicro Symposium on Digital System Design. s.n. (ed.). Piscataway: IEEE Society, p. 97-104 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. A multiported register file with register renaming for configurable softcore VLIW processors

    Anjam, F., Wong, JSSM. & Nadeem, MF., 2010, 2010 Intl. conf. on field programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A multipurpose clustering algorithm for task partitioning in multicore reconfigurable systems

    Ostadzadeh, SA., Meeuws, RJ., Sigdel, K. & Bertels, K., 2009, The international conference on complex, intelligent and software intensive systems. s.n. (ed.). Piscataway: IEEE Society, p. 663-668 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  23. A new approach to implement discrete wavelet transform using collaboration of reconfigurable elements

    Shahbahrami, A., Ahmadi, M., Wong, S. & Bertels, K., 2009, 2009 intl. conf. on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 344-349 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. A new digital architecture for reliable, ultra-low-power systems

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 350-355 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. A new latch-based threshold logic familiy

    Padure, MD., Cotofana, SD., Dan, C., Bodea, M. & Vassiliadis, S., 2001, CAS 2001: proceedings. Piscataway: IEEE Society, p. 531-534 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. A new model of placement quality measurement for online task placement

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 307-310 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. A novel HDL coding style to reduce power consumption for reconfigurable devices

    Thomas, TM., Theodoropoulos, D., Bertels, KLM. & Gaydadjiev, GN., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 295-299 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. A novel approach for accelerating the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z. & Nawaz, Z., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 40-45 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

    Thomas, TM., Hur, JY., Bertels, K. & Gaydadjiev, GN., 2010, 2010 IEEE 8th symp. on application specific processors. s.n. (ed.). CA, USA: IEEE Society, p. 105-110 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. A novel fast online placement algorithm on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 296-299 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. A novel flit serialization strategy to utilize partially faulty links in networks-on-chip

    Chen, C. & Lu, Y., 2012, 2012 Sixth IEEE/ACM international symposium on networks-on-chip. s.n. (ed.). New York: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. A novel productivity-driven logic element for field-programmable devices

    Marconi, T., Bertels, KLM. & Gaydadjiev, GN., 2014, In : International Journal of Electronics. 101, 6, p. 731-762 32 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. A padding processor for MPEG-4

    Kuzmanov, G., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 470-474 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. A parallel FPGA design of the Smith-waterman traceback

    Nawaz, Z., Nadeem, M., van Someren, J. & Bertels, KLM., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 454-459 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. A partially buffered crossbar packet switching architecture and its scheduling

    Mhamdi, LL., 2008, IEEE Intl. Symposium on Computers and Communications. s.n. (ed.). s.l.: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. A peer-to-peer agent auction

    Ogston, EFYL. & Vassiliadis, S., 2002, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part I. Castelfranchi, C. & Johnson, WL. (eds.). New York: Association for Computing Machinery (ACM), p. 151-159 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. A performance model for network processor architectures in packet processing system

    Ahmadi, M. & Wong, S., 2007, 19th IASTED Parallel and distributed computing and systems. Zheng SQ (ed.). Anaheim: ACTA Press, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. A platform for RFID security and privacy administration

    Rieback, M., Gaydadjiev, GN., Crispo, B., Hofman, R. F. H. & Tanenbaum, AS., 2006, Proc. 20th Large Installation System Administration Conf.. s.n. (ed.). Berkeley, USA: USENIX, p. 89-102 14 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. A polymorphic register file for matrix operations

    Ciobanu, CB., Kuzmanov, GK., Gaydadjiev, GN. & Ramirez, A., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 241-249 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. A power aware HW/SW partitioning for a DVB-H receiver module

    Koryfides, I., Cotofana, SD. & van Gassel, J., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 293-299 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. A practical scheduler for high-speed packet switches and internet routers

    Mhamdi, LL. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 398-403 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  43. A pragmatic gaze on stochastic resonance based variability tolerant memristance enhancement

    Ntinas, V., Rubio, A., Sirakoulis, G. C. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. 5 p. 8702792

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. A predictor-based power-saving policy for DRAM memories

    Thomas, G., Chandrasekar, K., Akesson, B., Juurlink, BHH. & Goossens, KGW., 2012, 15th Euromicro conference on digital system design. s.n. (ed.). s.n.: Euromicro, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. A profiling framework for design space exploration in heterogeneous systems context

    Sigdel, K., Meeuws, RJ. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 363-368 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. A proposal of a tile-based open GL compliant rasterization engine

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2002, Delft: Delft University of Technology. 123 p.

    Research output: Book/ReportReportProfessional

  48. A quantative prediction model for hardware/software partitioning

    Meeuws, RJ., Yankova, YD., Bertels, K., Gaydadjiev, GN. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 735-739 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. A reconfigurable baseband for 2.5G/3G and beyond

    Glossner, CJ., Iancu, D., Hokenek, E. & Moudgill, M., 2003, WWC'2003 Proceedings; proceedings of 2003 world wireless congress. s.n. (ed.). San Francisco: Delson Group Inc., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  50. A reconfigurable beamformer for audio applications

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 2009 IEEE 7th symposium on application specific processors. s.n. (ed.). Piscataway: IEEE Society, p. 80-87 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Previous 1 2 3 4 5 6 7 8 ...32 Next

ID: 19943