1. Binary multiplication based on Single Electron Tunneling

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 152-166 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  2. Bioinformatics specific cell BE ISA extensions

    Isaza, S. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 52-55 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Bit line coupling memory tests for single cell fails in SRAMs

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2010, 28th IEEE VLSI test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Bit-Flip Aware Control-Flow Error Detection

    Nazarian, G., Rodrigues, DG., Moreira, A., Carro, L. & Gaydadjiev, GN., 2015, Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2015. Daneshtalab, M., Aldinucci, M., Leppanen, V., Lilius, J. & Brorsson, M. (eds.). Piscataway: IEEE Society, p. 215-221 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Bitstream compression techniques for virtex 4 FPGAS

    Stefan, RA. & Cotofana, SD., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 323-328 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Block based compression storage expected performance

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, HPC 2000: proceeding. NJ Dimopoulos & KF Li (eds.). S.l.: Kluwer Academic Publishers, p. 389-406 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Bluetooth protocol profiling on the Xilinx Virtex II pro

    Campos Soares Borrego, F. & Wong, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 495-501 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. Boolean Logic Gate Exploration for Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2016, Proceedings - 11th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016. Danvers, MA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Branch instruction processor and method

    Blaner, B., Jeremiah, TL., Vassiliadis, S. & Williams, PG., 2000, Priority date 19 May 1999

    Research output: Patent

  11. Brownian Circuits: Designs

    Lee, J., Peper, F., Cotofana, S., Naruse, M., Ohtsu, M., Kawazoe, T., Takahashi, Y., Shimokawa, T., Kish, L. B. & Kubota, T., 2016, In : International Journal of Unconventional Computing. 12, 5-6, p. 341-362 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Buffer design trade-offs for single electron logic gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2005, Proceedings of 2005 5th IEEE Conference on Nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 433-436 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Buffered crossbar fabrics based on network on chip

    Mhamdi, LL., Goossens, KGW. & Varela Senin, I., 2010, 8th annual communication networks and services research conference. s.n. (ed.). Piscataway: IEEE Society, p. 74-79 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. Building blocks for MPEG stream processing

    Wong, JSSM., van Kester, J., Konstapel, M., Serra, R. & Visser, O., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 556-560 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. Building blocks for delay-insensitive circuits using single electron tunneling devices

    Safiruddin, S. & Cotofana, SD., 2007, 2007 7th IEEE international conference on nanotechnology. s.n. (ed.). Piscataway: IEEE Society, p. 704-708 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Building blocks for electron counting arithmetic

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 222-228 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. Building blocks for fluctuation based calculation in single electron tunneling technology

    Safiruddin, S., Cotofana, SD., Peper, F. & Lee, J., 2008, 2008 eighth IEEE conference on nanotechnology. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra

    Sendir, B., Govindaraju, M., Odaira, R. & Hofstee, P., 2018, 2018 IEEE 11th International Conference on Cloud Computing (CLOUD). Bilof, R. (ed.). Piscataway: IEEE, p. 220-228 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. CCproc: a custom VLIW cryptography co-processor for symmetric-key ciphers

    Theodoropoulos, D., Siskos, A. & Pnevmatikatos, DN., 2009, In : Lecture Notes in Computer Science. 5453, p. 318-323 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. CHOP: Haplotype-aware path indexing in population graphs

    Mokveld, T., Linthorst, J., Al-Ars, Z., Holstege, H. & Reinders, M., 2020, In : Genome biology. 21, 1, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. CIM-SIM: Computation in Memory SIMuIator

    Banagozar, A., Vadivel, K., Stuijk, S., Corporaal, H., Wong, S., Lebdeh, M. A., Yu, J. & Hamdioui, S., 27 May 2019, SCOPES'19: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems. Stuijk, S. (ed.). New York, NY: Association for Computing Machinery (ACM), p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. CIM100x: Computation in-Memory Architecture Based on Resistive Devices

    Hamdioui, S., Taouil, M., Du Nguyen, H. A., Haron, A., Xie, L. & Bertels, K., 2016, Proceedings of CNNA 2016: 15th International Workshop on Cellular Nanoscale and their Applications. Berlin: VDE, p. 95-96 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. CMOS implementation of generalized threshold functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2003, Computatational methods in neural modeling: seventh international work-conference on artificial and natural neural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 65-72 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. CMOS scaling impacts on reliability, what do we understand?

    Seyab, MSK., Haron, NZB. & Hamdioui, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 260-266 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. CONAN - a design exploration framework for reliable nano-electronics architectures

    Cotofana, SD., Schmid, A., Leblebici, Y., Ionescu, A., Soffke, O., Zipf, P., Glesner, M. & Rubio, A., 2005, Proceedings of the 16th IEEE International conference on Application-Specific Systems Architectures and Processors (ASAP). Vassiliadis, S., Dimopoulos, N. & Rajopadhye, S. (eds.). Los Alamitos: IEEE Society, p. 260-267 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  26. CORDIC scenario for Kalman-based channel estimation

    Sima, M., McGuire, M., Iancu, D. & Glossner, CJ., 2005, Proceedings of the IEEE Pacific Rim conference on communications, computers and signal processing. s.n. (ed.). Piscataway, USA: IEEE Society, p. 165-168 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  27. CORDIC-augmented sandbridge processor for channel equalization

    Sima, M., Glossner, CJ., Iancu, D., Ye, H., Iancu, A. & Hoane, AJ., 2005, Embedded computer systems: architectures, modeling, and simulation: 5th International workshop, SAMOS 2005. Hämäläinen, TD., Pimentel, AD., Takala, J. & Vassiliadis, S. (eds.). Heidelberg, Germany: Springer, p. 152-162 11 p. (Lecture Notes in Computer Science; vol. 3553).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. CRB analysis of the impact of unknown receiver noise on phased array calibration

    van der Tol, S. & Wijnholds, SJ., 2006, IEEE Workshop on Sensor Array and Multichannel Signal Processing, 2006. IEEE (ed.). Waltham, MA, USA: IEEE Society, p. 185-189 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Cache partitioning options for compositional multimedia applications

    Molnos, AM., Heijligers, MJM., Cotofana, SD. & van Eijndhoven, JTJ., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 86-90 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  30. Cache replacement policies for IP address lookups

    Guo, R., Delgado-Frias, JG. & Wong, S., 2007, 5th IASTEDintl. conf. on Circuits, Signals, and Systems. Delgado-Frias, J. G. (ed.). Zurich: ACTA Press, p. 70-75 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. Calculation of worst-case execution time for multicore processors using deterministic execution

    Mushtaq, H., Al-Ars, Z. & Bertels, K., 2015, Proceedings of the 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS. Reis, R. & Nunes de Lima, R. (eds.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Can SG-FET replace Fet in sleep mode circuits

    Enachescu, M., Cotofana, SD. & Tsamados, D., 2009, 4th international conference on Nano-Networks. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Capacitive threshold logic: a designer perspective

    Padure, MD., Dan, C., Cotofana, SD., Bodea, M. & Vassiliadis, S., 1999, CAS '99 proceedings. Vol. 1. S.l.: IEEE Society, p. 81-84 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip

    Ludovici, D., Gaydadjiev, GN., Bertozzi, D. & Benini, L., 2009, Proceedings of the 2009 Great Lakes symposium on VLSI. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 125-128 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Casta diva-a design for variability platform

    Cotofana, SD. & Meenderinck, CH., 2008, 2008 Intl. Semiconductor Conference. s.n. (ed.). s.l.: IEEE Society, p. 373-376 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. Centralized matchmaking - An empirical study

    Sigdel, K., Li, S., Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2005, Proceedings of the SAFE & ProRISC 2005. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 438-444 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Centralized matchmaking for minimal agents

    Bertels, K., Panchanathan, N., Vassiliadis, S. & Ebrahimi, BP., 2004, Proceedings of the 16th IASTED International conference Parallel and Distributed Computing and Systems. Gonzalez, T. (ed.). Anaheim: ACTA Press, p. 608-613 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Challenges and Solutions in Emerging Memory Testing

    Vatajelu, E. I., Prinetto, P., Taouil, M. & Hamdioui, S., 2019, In : IEEE Transactions on Emerging Topics in Computing. 7, 3, p. 493-506 14 p., 7894207.

    Research output: Contribution to journalArticleScientificpeer-review

  39. Challenges in exascale radio astronomy: Can the SKA ride the technologe wave?

    Vermij, E., Fiorin, L., Jongerius, R., Hagleitner, C. & Bertels, KLM., 2015, In : International Journal of High Performance Computing Applications. 29, 1, p. 37-50 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  40. Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation

    Zandrahimi, M., Al-Ars, Z., Debaud, P. & Castillejo, A., 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Teich, J. (ed.). Piscataway, NJ: IEEE, p. 1018-1019 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip

    Hansson, A., Coenen, M. & Goossens, KGW., 2007, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 149-154 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. Cluster-based Apache Spark implementation of the GATK DNA analysis pipeline

    Mushtaq, H. & Al-Ars, Z., 2015, Proceedings of the International Conference on Bioinformatics and Biomedicine. Huan, J., Miyano, S. & Shehu, A. (eds.). Piscataway: IEEE Society, p. 1471-1477 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Clustering on the move

    Roos, S., Corporaal, H. & Lamberts, R., 2002, MPCS '02 Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  44. Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs

    Wang, C., Li, X., Zhou, X., Chen, Y. & Bertels, K., 2014, p. 248-248. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  45. CoMPSoC: a template for composable and predictable multi-processor system on chips

    Hansson, A., Goossens, KGW., Bekooij, M. & Huisken, J., 2009, In : ACM Transactions on Design Automation of Electronic Systems. 14, 1, p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  46. CoMik: A predictable and cycle-accurately composable real-time microkernel

    Nelson, AT., Beyranvand Nejad, A., Molnos, AM., Koedam, M. & Goossens, KGW., 2014, Proceedings of the 2014 International Conference on Design, Automation & Test in Europe. Fettweis, G. & Nebel, W. (eds.). Leuven, Belgium: EDAA, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. Coarse reconfigurable multimedia unit extension

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. K Klöckner (ed.). Los Alamitos: IEEE, p. 235-242 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. Code deformation and lattice surgery are gauge fixing

    Vuillot, C., Lao, L., Criger, B., García Almudever, C., Bertels, K. & Terhal, B. M., 2019, In : New Journal of Physics. 21, 3, 21 p., 033028.

    Research output: Contribution to journalArticleScientificpeer-review

  49. Code generation and optimization for embedded processors

    Cilio, AGM., 2002, Genova, Italy: ECIG Edizioni Culturali Internazionali Genova. 174 p.

    Research output: ThesisDissertation (TU Delft)

  50. Code positioning for VLIW architectures

    Cilio, AGM. & Corporaal, H., 2001, HPCN Europe 2001: proceedings. G Goos & ... [et Al] (eds.). Berlin: Springer, p. 332-343 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Previous 1...4 5 6 7 8 9 10 11 ...32 Next

ID: 19943