1. Article › Scientific › Not peer-reviewed
  2. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  3. Agent-based social simulation in markets

    Bertels, KLM. & Boman, M., 2001, In : Electronic Commerce Research. 1, 1-2, p. 149-158 10 p.

    Research output: Contribution to journalArticleScientific

  4. An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, In : SIGARCH Computer Architecture News. 44, 4, p. 38-43 6 p.

    Research output: Contribution to journalArticleScientific

  5. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  6. Heterogeneous trading agents

    Neuberg, L. & Bertels, KLM., 2003, In : Complexity. 8, 5, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientific

  7. JAVA signal processing: FFTs with bitecodes

    Glossner, CJ., Thilo, J. & Vassiliadis, S., 2000, In : Concurrency: Practice and Experience. 10, 11-13, p. 1173-1178 6 p.

    Research output: Contribution to journalArticleScientific

  8. Link-time effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 2000, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 16, p. 503-511 9 p.

    Research output: Contribution to journalArticleScientific

  9. Multihierarchical intelligent simulation

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2001, In : Polytechnical University of Bucharest. Scientific Bulletin. Series C: Electrical Engineering and Computer Science. 63, 4, p. 15-24 10 p.

    Research output: Contribution to journalArticleScientific

  10. Parallel computer architecture and instruction-level parallelism

    Vassiliadis, S., Dimopoulos, N., Collard, JF. & Bode, A., 2003, In : Lecture Notes in Computer Science. p. 541-542 2 p.

    Research output: Contribution to journalArticleScientific

  11. Signed digit addition and related operations with threshold logic

    Cotofana, SD. & Vassiliadis, S., 2000, In : IEEE Transactions on Computers. 49, 3, p. 193-207 15 p.

    Research output: Contribution to journalArticleScientific

  12. The -Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, In : Journal of Lightwave Technology. 18, 8, p. 1049-1063 15 p.

    Research output: Contribution to journalArticleScientific

  13. Article › Scientific › Peer-reviewed
  14. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. A Microarchitecture for a Superconducting Quantum Processor

    Fu, X., Rol, M. A., Bultink, C. C., van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., Almudéver, C. G., DiCarlo, L. & Bertels, K., 2018, In : IEEE Micro. 38, 3, p. 40-47 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. A control microarchitecture for fault-tolerant quantum computing

    Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

    Medeiros, G. C., Bolzani Poehls, L. M., Taouil, M., Luis Vargas, F. & Hamdioui, S., 2018, In : Microelectronics Reliability. 88-90, p. 355-359 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

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