1491 - 1500 out of 1,593Page size: 10
  1. Patent › Other research output
  2. Power control of a processor using hardware structures controlled by a compiler with an accumulated instruction profile

    Altman, ER., Glossner, CJ., Hokenek, E., Meltzer, D. & Moudgill, M., 2003, Patent No. US 2002/0112193 A1, Priority date 15 Aug 2002

    Research output: Patent

  3. System and method including distributed instruction buffers holding a second instruction form

    Altman, ER., Glossner, CJ., Hokenek, E. & Moudgill, M., 2003, Patent No. US 2002/0161987 A1, Priority date 31 Oct 2002

    Research output: Patent

  4. System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction

    Vassiliadis, S., Blaner, B. & Jeremiah, TL., 2000, Priority date 28 Jun 2000

    Research output: Patent

  5. Book › Scientific › Not peer-reviewed
  6. Acceleration of Bioinformatics Sequence Alignment - A Hardware Perspective

    Hasan, L., 2011, Germany: LAP LAMBERT Academic Publishing. 132 p.

    Research output: Book/ReportBookScientific

  7. Scalable parallel programming applied to H.264/AVC decoding

    Juurlink, BHH., Alvarez, M., Chi, C., Pereira de Azevedo Filho, AP., Meenderinck, CH. & Ramirez, A., 2012, Berlin: Springer. 95 p.

    Research output: Book/ReportBookScientific

  8. Testing static random access memories - Defects, fault models and test patters

    Hamdioui, S., 2004, Boston: Kluwer Academic Publishers. 240 p.

    Research output: Book/ReportBookScientific

  9. Book › Professional
  10. 2007 International conference on field programmable logic and applications

    Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

    Research output: Book/ReportBookProfessional

  11. Design & Technology of Integrated Systems in Nanoscala era

    Hamdioui, S. & Orailoglu, A., 2007, Piscataway: IEEE Society. 260 p.

    Research output: Book/ReportBookProfessional

ID: 19943