1. Article › Scientific › Not peer-reviewed
  2. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  3. Agent-based social simulation in markets

    Bertels, KLM. & Boman, M., 2001, In : Electronic Commerce Research. 1, 1-2, p. 149-158 10 p.

    Research output: Contribution to journalArticleScientific

  4. An Efficient GPU-Accelerated Implementation of Genomic Short Read Mapping with BWA-MEM

    Houtgast, E., Sima, V., Bertels, K. & Al-Ars, Z., 2016, In : SIGARCH Computer Architecture News. 44, 4, p. 38-43 6 p.

    Research output: Contribution to journalArticleScientific

  5. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  6. Heterogeneous trading agents

    Neuberg, L. & Bertels, KLM., 2003, In : Complexity. 8, 5, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientific

  7. JAVA signal processing: FFTs with bitecodes

    Glossner, CJ., Thilo, J. & Vassiliadis, S., 2000, In : Concurrency: Practice and Experience. 10, 11-13, p. 1173-1178 6 p.

    Research output: Contribution to journalArticleScientific

  8. Link-time effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 2000, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 16, p. 503-511 9 p.

    Research output: Contribution to journalArticleScientific

  9. Multihierarchical intelligent simulation

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2001, In : Polytechnical University of Bucharest. Scientific Bulletin. Series C: Electrical Engineering and Computer Science. 63, 4, p. 15-24 10 p.

    Research output: Contribution to journalArticleScientific

  10. Parallel computer architecture and instruction-level parallelism

    Vassiliadis, S., Dimopoulos, N., Collard, JF. & Bode, A., 2003, In : Lecture Notes in Computer Science. p. 541-542 2 p.

    Research output: Contribution to journalArticleScientific

  11. Signed digit addition and related operations with threshold logic

    Cotofana, SD. & Vassiliadis, S., 2000, In : IEEE Transactions on Computers. 49, 3, p. 193-207 15 p.

    Research output: Contribution to journalArticleScientific

  12. The -Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, In : Journal of Lightwave Technology. 18, 8, p. 1049-1063 15 p.

    Research output: Contribution to journalArticleScientific

  13. Article › Scientific › Peer-reviewed
  14. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. A Microarchitecture for a Superconducting Quantum Processor

    Fu, X., Rol, M. A., Bultink, C. C., van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., Almudéver, C. G., DiCarlo, L. & Bertels, K., 2018, In : IEEE Micro. 38, 3, p. 40-47 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. A Survey and Evaluation of FPGA High-Level Synthesis Tools

    Nane, R., Sima, VM., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, YT., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J. & Bertels, K., 2016, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 35, 10, p. 1591-1604 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. A control microarchitecture for fault-tolerant quantum computing

    Fu, X., Lao, L., Bertels, K. & Almudever, C. G., 2019, In : Microprocessors and Microsystems. 70, p. 21-30 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

    Medeiros, G. C., Bolzani Poehls, L. M., Taouil, M., Luis Vargas, F. & Hamdioui, S., 2018, In : Microelectronics Reliability. 88-90, p. 355-359 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  22. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  23. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  24. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  25. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  26. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  27. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  29. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  31. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  32. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. A novel productivity-driven logic element for field-programmable devices

    Marconi, T., Bertels, KLM. & Gaydadjiev, GN., 2014, In : International Journal of Electronics. 101, 6, p. 731-762 32 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. A software-defined communications baseband design

    Glossner, CJ., Iancu, D., Lu, J., Hokenck, E. & Moudgill, M., 2003, In : IEEE Communications Magazine. 41, 1, p. 4-12 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  35. A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

    van de Goor, AJ. & Tlili, IBS., 2003, In : IEEE Transactions on Computers. 52, 10, p. 1320-1330 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  36. A unified execution model for multiple computation models of streaming applications on a composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, In : Journal of Systems Architecture. 59, 10, part C, p. 1032-1046 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  37. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  38. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

    Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 61-73 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  39. Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

    Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

    Research output: Contribution to journalArticleScientificpeer-review

  40. Adaptive fault-tolerant architecture for unreliable technologies with heterogenous variability

    Aymerich, N., Cotofana, SD. & Rubio, A., 2012, In : IEEE Transactions on Nanotechnology. 11, 4, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Addition related arithmetic operations via controlled transport of charge

    Cotofana, SD., Lageweg, CR. & Vassiliadis, S., 2005, In : IEEE Transactions on Computers. 54, 3, p. 243-256 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  42. Addressing GPU on-chip shared memory bank conflicts using elastic pipeline

    Gou, C. & Gaydadjiev, GN., 2013, In : International Journal of Parallel Programming. 41, 3, p. 400-429 30 p.

    Research output: Contribution to journalArticleScientificpeer-review

  43. Alternative architectures toward reliable memristive crossbar memories

    Vourkas, I., Stathis, D., Sirakoulis, G. C. & Hamdioui, S., 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 206-217 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  44. An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1},

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 8, p. 1500-1503 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  45. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  46. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  47. An analysis of limited wavelength translation in regular all-optical WDM networks

    Sharma, A. & Varvarigos, EA., 2001, In : Journal of Lightwave Technology. 18, 12, p. 1606-1619 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  48. An analysis of oblivious and adaptive routing in optical networks with wavelength translation

    Lang, JP., Sharma, A. & Varvarigos, EA., 2001, In : IEEE - ACM Transactions on Networking. 9, 4, p. 503-517 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  49. An industrial evaluation of DRAM tests

    van de Goor, AJ., 2004, In : IEEE Design & Test of Computers. 21, 5, p. 430-440 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  50. Analog-to-digital converter based on single-electron tunneling transistors

    Hu, C., Cotofana, SD., Jiang, J. & Cai, Q., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 11, p. 1209-1213 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  51. Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics

    Veneman, WJ., de Sonneville, J., van der Kolk, KJ., Ordas, A., Al-Ars, Z., Meijer, AH. & Spaink, HP., 2015, In : Immunogenetics. 67, 3, p. 135-147 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  52. Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

    Wang, Y., Cotofana, SD. & Fang, L., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2521-2529 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  53. Ant colony inspired microeconomic based resource management in ad hoc grids

    Abdullah, MT., Bertels, K. & Onana Alima, L., 2009, In : Lecture Notes in Computer Science. 5529, p. 189-198 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  54. Architectural support for 3D graphics in the complex streamed instruction set

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2002, In : International Journal of Parallel and Distributed Systems & Networks. 5, 4, p. 185-193 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  55. Architecture enhancements for the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., de Sutter, B. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 66-81 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  56. Auction protocols for resource allocations in ad-hoc grids

    Pourebrahimi, B. & Bertels, KLM., 2008, In : Lecture Notes in Computer Science. LNCS5168, p. 520-533 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  57. Avoiding conversion and rearrangements overhead in SIMD architectures

    Shahbahrami, A., Juurlink, B., Borodin, D. & Vassiliadis, S., 2006, In : International Journal of Parallel Programming. 34, 3, p. 237-260 24 p.

    Research output: Contribution to journalArticleScientificpeer-review

  58. BRAM-LUT tradeoff on a polymorphic DES design

    Chaves Fernandes, R., Donchev, B., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 55-65 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  59. Badwidth analysis of functional interconnects used as test access mechanism

    van den Berg, A., Ren, P., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2010, In : Journal of Electronic Testing: theory and applications. 26, 4, p. 453-464 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  60. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  61. Brownian Circuits: Designs

    Lee, J., Peper, F., Cotofana, S., Naruse, M., Ohtsu, M., Kawazoe, T., Takahashi, Y., Shimokawa, T., Kish, L. B. & Kubota, T., 2016, In : International Journal of Unconventional Computing. 12, 5-6, p. 341-362 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  62. CCproc: a custom VLIW cryptography co-processor for symmetric-key ciphers

    Theodoropoulos, D., Siskos, A. & Pnevmatikatos, DN., 2009, In : Lecture Notes in Computer Science. 5453, p. 318-323 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  63. CHOP: Haplotype-aware path indexing in population graphs

    Mokveld, T., Linthorst, J., Al-Ars, Z., Holstege, H. & Reinders, M., 2020, In : Genome biology. 21, 1, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  64. Challenges and Solutions in Emerging Memory Testing

    Vatajelu, E. I., Prinetto, P., Taouil, M. & Hamdioui, S., 2019, In : IEEE Transactions on Emerging Topics in Computing. 7, 3, p. 493-506 14 p., 7894207.

    Research output: Contribution to journalArticleScientificpeer-review

  65. Challenges in exascale radio astronomy: Can the SKA ride the technologe wave?

    Vermij, E., Fiorin, L., Jongerius, R., Hagleitner, C. & Bertels, KLM., 2015, In : International Journal of High Performance Computing Applications. 29, 1, p. 37-50 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  66. CoMPSoC: a template for composable and predictable multi-processor system on chips

    Hansson, A., Goossens, KGW., Bekooij, M. & Huisken, J., 2009, In : ACM Transactions on Design Automation of Electronic Systems. 14, 1, p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  67. Code deformation and lattice surgery are gauge fixing

    Vuillot, C., Lao, L., Criger, B., García Almudever, C., Bertels, K. & Terhal, B. M., 2019, In : New Journal of Physics. 21, 3, 21 p., 033028.

    Research output: Contribution to journalArticleScientificpeer-review

  68. Collaboration of reconfigurable processors in grid computing: Theory and application

    Ahmadi, M., Shahbahrami, A. & Wong, JSSM., 2011, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 27, 6, p. 850-859 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  69. Comparative analysis of soft and hard on-chip interconnects for FPGAs

    Hur, JY., Goossens, KGW., Mhamdi, L. & Wahlah, MA., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  70. Comparing Neural Network Based Decoders for the Surface Code

    Varsamopoulos, S., Bertels, K. & Almudever, C. G., 1 Feb 2020, In : IEEE Transactions on Computers. 69, 2, p. 300-311 12 p., 8880492.

    Research output: Contribution to journalArticleScientificpeer-review

  71. Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates

    Kukner, H., Khan, F., Weckx, P., Raghavan, P., Hamdioui, S., Kaczer, B., Catthoor, F., van der Perre, L., Lauwereins, R. & Groeseneken, G., 2014, In : IEEE Transactions on Device and Materials Reliability. 14, 1, p. 182-193 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  72. Compositional, dynamic cach management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD., Heijligers, MJM. & van Eijndhoven, JTJ., 2009, In : Journal of Signal Processing Systems: the journal of DSPtechnologies. 57, 2

    Research output: Contribution to journalArticleScientificpeer-review

  73. Computing division using single-electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : IEEE Transactions on Nanotechnology. 6, 4, p. 451-459 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. Context aware slope based transistor-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  75. Controlled degradation stochastic resonance in adaptive averaging cell based architectures

    Aymerich, N., Cotofana, SD. & Rubio, A., 2013, In : IEEE Transactions on Nanotechnology. 12, 6, p. 888-896 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  76. Controlling a complete hardware synthesis toolchain with LARA aspects

    Cardoso, JMP., Carvalho, T., Coutinho, JGF., Nobre, R., Nane, R., Diniz, P., Petrov, Z., Luk, W. & Bertels, KLM., 2013, In : Microprocessors and Microsystems. 37, 8, p. 1073-1089 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  77. Cost-efficient SHA hardware accelerators

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 999-1008 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  78. Critical transistors nexus based circuit-level aging assessment and prediction

    Cucu Laurenciu, N. & Cotofana, SD., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2512-2520 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  79. Cross-layer designs architecture for LEO satellite ad hoc network

    Chang, Z. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. 5031, p. 164-176 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  80. Custom architecture for multicore audio Beamforming systems

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2013, In : ACM Transactions on Embedded Computing Systems. 13, 2, p. 1-26 26 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

    Hur, JY., Stefanov, TP., Wong, JSSM. & Goossens, KGW., 2012, In : IET Computers and Digital Techniques. 6, 1, p. 59-68 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  82. DOPA: GPU-based protein alignment using database and memory access optimizations

    Hasan, L., Kentie, M. & Al-Ars, Z., 2011, In : BMC Research Notes. 4:261, p. 1-11 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  83. Defect and Fault Modeling Framework for STT-MRAM Testing

    Wu, L., Rao, S., Taouil, M., Cardoso Medeiros, G., Fieback, M., Marinissen, E. J., Kar, G. S. & Hamdioui, S., 17 Dec 2019, In : IEEE Transactions on Emerging Topics in Computing. 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  84. Dependable multicore architectures at nanoscale: The view from Europe

    Ottavi, M., Pontarelli, S., Gizopoulos, D., Paschalis, A., Bolchini, C., Michael, MK., Anghel, L., Tahoori, M., Reviriego, P., Bringmann, O., Izosimov, V., Manhaeve, H., Strydis, C. & Hamdioui, S., 2015, In : IEEE Design & Test of Computers. 32, 2, p. 17-28 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  85. Design and implementation of an operating system for composable processor sharing

    Hansson, A., Molnos, AM., Nelson, AT., Ambrose, JA. & Goossens, KGW., 2011, In : Microprocessors and Microsystems. 35, p. 246-260 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  86. Design and performance evaluation of an adaptive FPGA for network applications

    Kachris, C., Wong, S. & Vassiliadis, S., 2009, In : Microelectronics Journal. 40, 7, p. 1103-1110 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  87. Design trade-offs in customized on-chip crossbar schedulers

    Hur, JY., Wong, S. & Stefanov, TP., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  88. Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-issue VLIW Processor

    Sartor, A. L., Becker, P. H. E., Hoozemans, J., Wong, S. & Beck, A. C. S., 2018, In : IEEE Transactions on Multi-Scale Computing Systems. 4, 3, p. 327-339 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  89. Dynamic faults in random-access-memories: concept, fault models and tests

    Hamdioui, S., Al-Ars, Z., van de Goor, AJ. & Rodgers, M., 2003, In : Journal of Electronic Testing: theory and applications. 19, 2, p. 195-205 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  90. Editorial Note on Memristor Models, Circuits and Architectures

    Sirakoulis, G. C. & Hamdioui, S., 2016, In : International Journal of Unconventional Computing. 12, 4, p. 247-250 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Efficent and highly portable deterministic multithreading (DetLock)

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2013, In : Computing. 95, p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  92. Efficient Acceleration of the Pair-HMMs Forward Algorithm for GATK HaplotypeCaller on Graphics Processing Units

    Ren, S., Bertels, K. & Al-Ars, Z., 2018, In : Evolutionary Bioinformatics. 14, p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  93. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2012, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 59, 2, p. 636-657 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  94. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2010, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 52, 3

    Research output: Contribution to journalArticleScientificpeer-review

  95. Efficient multicast support in high-speed packet switches

    Mhamdi, LL., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of Networks. 2, 3, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  96. Efficient task scheduling for runtime reconfigurable systems

    Fazlali, M., Sabeghi, M., Zakerolhosseini, A. & Bertels, KLM., 2010, In : Journal of Systems Architecture. 56, 11, p. 623-632 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  97. Efficient tests for realistic faults in dual-port SRAMS

    Hamdioui, S. & van de Goor, AJ., 2002, In : IEEE Transactions on Computers. 51, 5, p. 460-474 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  98. Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

    Hansson, A., Wiggers, M., Moonen, A., Goossens, KGW. & Bekooij, M., 2009, In : IET Computers and Digital Techniques. 3, 5, p. 398-412 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  99. Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

    Majzoub, S., Saleh, R. A., Ashraf, I., Taouil, M. & Hamdioui, S., 2019, In : IEEE Access. 7, p. 33115-33129 15 p., 8648367.

    Research output: Contribution to journalArticleScientificpeer-review

  100. Enhancing PUF based challenge-response sets by exploiting various background noise configurations

    Martin, H., Peris-Lopez, P., Di Natale, G., Taouil, M. & Hamdioui, S., 2019, In : Electronics (Switzerland). 8, 2, p. 1-14 14 p., 145.

    Research output: Contribution to journalArticleScientificpeer-review

  101. Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2019, In : Journal of Electronic Testing: Theory and Applications (JETTA). 35, 3, p. 303-315 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  102. Experimental error mitigation via symmetry verification in a variational quantum eigensolver

    Sagastizabal, R., Bonet-Monroig, X., Singh, M., Rol, M. A., Bultink, C. C., Fu, X., Ostroukh, V. P., Muthusubramanian, N., Bruno, A., Beekman, M., Haider, N., O'Brien, T. E. & Dicarlo, L., 2019, In : Physical Review A. 100, 1, 6 p., 010302.

    Research output: Contribution to journalArticleScientificpeer-review

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