401 - 500 out of 1,593Page size: 100
  1. Conference contribution › Scientific › Not peer-reviewed
  2. Soft faults and the importance of stresses in memory testing

    Al-Ars, Z. & van de Goor, AJ., 2004, Design, automation and test in Europe; Date04 Proceedings. Gielen, G. & Figueras, J. (eds.). Piscataway: IEEE Society, p. 1084-1091 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  3. Sparse matrix vector multiplication evaluation using the BBCS scheme

    Stathis, P., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 1. Y Manolopoulos & S Evripidou (eds.). S.l.: s.n., p. 40-49 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. Synthesis of regular expressions targeting FPGAs: current status and open issues

    Bispo, JCVM., Sourdis, I., Cardoso, JMP. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 179-190 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  5. Synthetic benchmark generator for the MOLEN processor

    Wong, JSSM., Luo, G. & Cotofana, SD., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 561-567 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  6. Systematic customization of on-chip crossbar intervconnects

    Hur, JY., Stefanov, TP., Wong, S. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 61-72 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. TTL inter-task communication implementation on a shared-memory multiprocessor platform

    Li, B., van der Wolf, P. & Bertels, K., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 390-397 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. The Artemis architecture workbench

    Pimentel, AD., van der Wolf, P., Deprettere, EFA., Hertzberger, LO., van Eijndhoven, JTJ. & Vassiliadis, S., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 53-62 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. The Fidelity Slider: A User-Defined Method to Trade off Accuracy for Performance in Canny Edge Detector

    Kritchallo, V., Vermij, E., Bertels, K. & Al-Ars, Z., 2016, 11th HiPEAC conference. p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. The ManArray embedded processor architecture

    Pechanek, GG. & Vassiliadis, S., 2000, Proceedings, vol. 1. F Vajda (ed.). Los Alamitos: IEEE, p. 348-355 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  11. The \-scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 1999, Proceedings. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  12. The impact of code positioning on ILP scheduling

    Cilio, AGM. & Corporaal, H., 2000, ASCI 2000 proceedings. LJ Vliet, V. (ed.). Delft: Advanced School for Computing and Imaging, p. 37-44 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  13. The lambda-Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, Proceedings thirty-seventh annual Allerton conference on communication, control and computing. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  14. The molen programming paradigm

    Vassiliadis, S., Gaydadjiev, GN., Bertels, KLM. & Panainte, E., 2003, Third international workshop on systems, architectures, modeling, and simulation. Leiden: SAMOS Initiative, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. The priority broadcast scheme for dynamic broadcast in hypercubes and related networks

    Yeh, CH., Varvarigos, EA. & Lee, H., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 294-301 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  16. The recursive grid layout scheme for VLSI layout of hierarchical networks

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999 Proceedings. Los Alamitos: IEEE, p. 441-445 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  17. The scalable networking scheme for high-speed networks

    Yeh, CH. & Varvarigos, EA., 2000, ICC 2000 conference record: global convergence through communications. Piscataway: IEEE Society, p. 1335-1342 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  18. The universal multiplier unit

    Calderón, H. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 341-346 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  19. Trading efficiency for energy in a texture cache architecture

    Antochi, I., Juurlink, BHH., Cilio, AGM. & Liuha, P., 2002, Proceedings of the 2002 Euromicro conference on Massively-parallel computing systems. Fort Collins, Colorado, USA: The National Technological University Press, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  20. USB enabled PDP8 computer

    van de Pol, J., Mul, MP., Gaydadjiev, GN. & Vassiliadis, S., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 112-117 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  21. Unstructured agent matchmaking: experiments in timing and fuzzy matching

    Ogston, EFYL. & Vassiliadis, S., 2002, Applied computing 2002: Proceedings of the 2002 ACM symposium on applied computing. New York: Association for Computing Machinery (ACM), p. 300-306 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  22. VLSI layout and packaging of butterfly networks

    Yeh, CH., Parhami, B., Varvarigos, EA. & Lee, H., 2000, SPAA 2000. New York: Association for Computing Machinery (ACM), p. 196-205 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  23. Wireless SDR solutions: The challenge and promise of next generation handsets

    Glossner, CJ., Hokenek, E. & Moudgill, M., 2002, CDC 2002 Communications Design Conference Proceedings. CMP Media LLC, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  24. Y'UV-to-R'G'B' color space conversion on FPGA-augmented TriMedia-32 processor

    Sima, M., Vassiliadis, S., van Eijndhoven, JTJ. & Cotofana, SD., 2002, Proceeding ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 465-471 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  25. ¿MOS enhanced differential current-switch threshold logic gates

    Li, KC., Padure, MD. & Cotofana, SD., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 530-535 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  26. Conference contribution › Scientific › Peer-reviewed
  27. (When) will CMPs hit the power wall?

    Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. 3-Tier reconfiguration model for FPGAs using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 504-509 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. 3D graphics benchmarks for low-power architectures

    Antochi, I., Juurlink, BHH., Vassiliadis, S. & Liuha, P., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 18-22 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  31. 3D graphics tile-based systolic scan-conversion

    Crisu, D., Vassiliadis, S., Cotofana, SD. & Liuha, P., 2004, Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on. Matthews, MB. (ed.). Piscataway: IEEE Society, p. 517-521 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. 3D stacked wide-operand adders: A case study

    Voicu, GR., Lefter, M., Enachescu, M. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA, USA: IEEE, p. 133-141 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. 3D-COSTAR: a cost model for 3D stacked ICs

    Taouil, M., Hamdioui, S., Marinissen, EJ. & Bhawmik, S., 2012, Proceedings Third IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits. Zorian, Y., Marijnissen, E. & Hamdioui, S. (eds.). Los Alamitos, CA, USA: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  34. 64-bit floating-point FPGA matrix multiplication

    Dou, Y., Vassiliadis, S., Kuzmanov, GK. & Gaydadjiev, GN., 2005, Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays (FPGA '05). s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 86-95 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

    Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. A 3D-audio reconfigurable processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. A Comparison of Seed-and-Extend Techniques in Modern DNA Read Alignment Algorithms

    Ahmed, N., Bertels, K. & Al-Ars, Z., Dec 2016, 2016 IEEE International Conference on Bioinformatics and Biomedicine (BIBM). Tian, T., Jiang, Q., Liu, Y., Burrage, K., Song, J., Wang, Y., Hu, X., Morishita, S., Zhu, Q. & Wang, G. (eds.). Piscataway, NJ: IEEE, p. 1421-1428 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. A Computation-In-Memory Accelerator Based on Resistive Devices

    Du Nguyen, H. A., Yu, J., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 2019, Proceedings of the International Symposium on Memory Systems. New York: Association for Computing Machinery (ACM), p. 19-32 14 p. (ICPS: ACM International Conference Proceeding Series).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  40. A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

    Medeiros, G. C., Cem Gursoy, C., Wu, L., Fieback, M., Jenihhin, M., Taouil, M. & Hamdioui, S., 2020, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). Institute of Electrical and Electronics Engineers (IEEE), p. 792-797 6 p. 9116278. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  41. A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons

    Yu, J., Hogervorst, T. & Nane, R., 2017, GLSVLSI '17 Proceedings of the on Great Lakes Symposium on VLSI 2017 . New York: Association for Computing Machinery (ACM), p. 71-76 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model

    Fang, J., Chen, J., Lee, J., Al-Ars, Z. & Hofstee, P., 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): Proceedings. IEEE, p. 335-335 1 p. 8735518

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. A Heterogeneous Quantum Computer Architecture

    Fu, X., Riesebos, L., Lao, L., García Almudever, C., Sebastiano, F., Versluis, R., Charbon, E. & Bertels, K., 2016, Proceedings of the ACM International Conference on Computing Frontiers, CF '16. New York: Association for Computing Machinery (ACM), p. 323-330 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  45. A Markovian, variation-aware circuit-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, International symposium on nanoscale architectures. s.n. (ed.). New York: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. A Non-Intrusive Online FPGA Test Scheme Using A Hardwired Network on Chip

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 351-359 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. A Novel Dynamic Task Scheduling Algorithm for Grid Networks with Reconfigurable Processors

    Nadeem, MF., Ostadzadeh, SA., Ahmadi, M., Nadeem, M. & Wong, JSSM., 2011, 5th HiPEAC Workshop on Reconfigurable Computing. s.n. (ed.). s.l.: HiPEAC, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  48. A Novel Virtual Age Reliability Model for Time-toFailure Prediction

    Wang, Y. & Cotofana, SD., 2010, IEEE International Integrated Reliability Workshop Final Report. Young, C. & Geilenkeuser, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 102-105 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  49. A Reconfigurable Audio Beamforming Multi-Core Processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Symposium on Applied Reconfigurable Computing. Koch, A., Krishnamurthy, R., McAllister, J., Woods, R. & El-Ghazawi, T. (eds.). Heidelberg: Springer, p. 3-14 12 p. (Lecture Notes in Computer Science; vol. 6578).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. A Security Verification Template to Assess Cache Architecture Vulnerabilities

    Ghasempouri, T., Raik, J., Paul, K., Reinbrecht, C., Hamdioui, S. & Taouil, M., 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): Proceedings. IEEE, p. 1-6 6 p. 9095707

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. A Simulation Framework for Reconfigurable Processors in Large-scale Distributed Systems

    Nadeem, MF., Ostadzadeh, SA., Nadeem, M., Wong, JSSM. & Bertels, KLM., 2011, International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Sheu, JP. & Wang, CL. (eds.). Piscataway: IEEE Society, p. 352-360 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

    Yang, B., Popovici, E., Quille, M. A., Amann, A. & Cotofana, S., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 79-84 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  53. A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2011, Proceedings 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 818-822 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. A Uni¿ed Aging Model of NBTI and HCI Degradation towards Lifetime Reliability Management for Nanoscale MOSFET Circuits

    Wang, Y., Cotofana, SD. & Fang, L., 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures. Moritz, CA. & O'Connor, I. (eds.). Piscataway, NJ, USA: IEEE Society, p. 175-180 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. A VLIW softcore processor with dynamically adjustable issue-slots

    Anjam, F., Nadeem, M. & Wong, JSSM., 2010, 2010 intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. A cache architecture for counting bloom filters

    Ahmadi, M. & Wong, S., 2007, 15th International conference on networks. s.n. (ed.). Piscataway: IEEE Society, p. 218-223 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. A case for hardware task management support for the StarSS programming

    Meenderinck, CH. & Juurlink, BHH., 2010, 13th Euromicro conf. on digital systems design, architectures, methods and tools. s.n. (ed.). Piscataway: IEEE Society, p. 347-354 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. A comparison of two SIMD implementations of the 2D discrete wavelet transform

    Shahbahrami, A. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 169-177 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. A composable, energy-managed, realtimeMPSOC platform

    Goossens, KGW., Molnos, AM., Ambrose, JA., Nelson, AT., Stefan, RA. & Cotofana, SD., 2010, 12th Intl. optimization electrical and electronic equipment. s.n. (ed.). s.l.: IEEE Society, p. 870-876 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. A direct measurement scheme of amalgamated aging effects with novel on-chip sensor

    Cucu Laurenciu, N. & Cotofana, SD., 2013, 21st IFIP/IEEE international conference on very large scale integration. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. A drift-reduced hierarchical wavelet coding scheme for scalable video transmissions

    Choupani, R., Wong, S. & Tolun, MR., 2009, The first international conference on advances in multimedia. Burdescu, DD., Crespi, N. & Dini, O. (eds.). Piscataway: IEEE Society, p. 68-73 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. A dynamic pricing and bidding strategy for autonomous agents in grids

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2007, 6th international joint conference on autonomous agents and multi-agent systems. Joseph S Bergamaschi S, D. Z. (ed.). s.l.: s.l., p. 70-81 12 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. A dynamically reconfigurable queue scheduler

    Kachris, C. & Vassiliadis, S., 2006, 2006 International conference on Field Programmable Logic and Applications. Koch, A., Leong, P. & Boemo, E. (eds.). Piscataway: IEEE Society, p. 869-872 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. A fast CRC update implementation

    Lu, W. & Wong, JSSM., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 113-120 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. A fault primitive based analysis of dynamic memory faults

    Hamdioui, S., Gaydadjiev, GN. & van de Goor, AJ., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 84-89 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. A fault primitive based analysis of linked faults in RAMs

    Al-Ars, Z., Hamdioui, S. & van de Goor, AJ., 2003, MTDT 2003; Records of the 2003 international workshop on memory technology, design and testing. s.n. (ed.). Piscataway: IEEE Society, p. 33-39 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. A flexible simulator of pipelined processors

    Juurlink, BHH., Bertels, KLM. & Li, B., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 483-493 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. A framework for adaptive matchmaking in distributed computing

    Sigdel, K., Bertels, K., Pourebrahimi, B., Vassiliadis, S. & Shuai, Y., 2005, Proceedings of GRID workshop Cracow-04. Bubak, M., Turala, M. & Wiatr, K. (eds.). Kraków: Cyfronet AGH, p. 150-157 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. A full adder implementation using SET based linear threshold gates

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. Baric, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 665-669 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. A fully dynamic reconfigurable NoC-based MPSoC: the advantages of total reconfiguration

    Santos, PC., Nazar, GL., Anjam, F., Wong, JSSM., Matos, D. & Carro, L., 2013, 7th HiPEAC workshop on reconfigurable computing. s.n. (ed.). Berlin: Springer, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. A generic digital architecture & compiler for implantable devices

    Strydis, C., Gaydadjiev, GN. & Vassiliadis, S., 2005, Symposium proceedings Architectures and compilers for embedded systems (ACES). s.n. (ed.). Gent: Academia Press, p. 69-72 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. A hardware cache memcpy accelerator

    Wong, JSSM., Campos Soares Borrego, F. & Vassiliadis, S., 2006, International Conference on Field Programmable Technology. s.n. (ed.). Piscataway: IEEE Society, p. 141-147 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. A hardware implementation of the unisim pipeline model

    Stefan, RA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 259-263 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems

    Pham Quoc Cuong, P., Al-Ars, Z. & Bertels, KLM., 2012, Conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. A hierarchical sparse matrix storage format for vector processors

    Stathis, PT., Vassiliadis, S. & Cotofana, SD., 2003, IPDPS 2003; 17th international parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. A high-level debug environment for communication-centric debug

    Goossens, KGW., Vermeulen, B. & Beyranvand Nejad, A., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 202-207 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

    Nadeem, M., Wong, S., Kuzmanov, GK. & Shabbir, A., 2009, 2009 IEEE/ACM/IFIP 7th workshop on embedded for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 18-27 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  82. A hybrid cross layer architecture for wireless protocol stacks

    Chang, Z. & Gaydadjiev, GN., 2008, 2008 international wireless communications and mobile computing conference. s.n. (ed.). Piscataway: IEEE Society, p. 279-285 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

    Strano, A., Ludovici, D. & Bertozzi, D., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 20-27 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. A lightweight speculative and predicative scheme for hardware execution

    Nane, R., Sima, VM. & Bertels, KLM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). New York: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 283-293 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. A linear threshold gate implemantation in single electron technology

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. A Jacobs (ed.). Los Alamitos: IEEE, p. 93-98 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. A load/store unit for a memcpy hardware accelerator

    Vassiliadis, S., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 537-541 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. A low cost method to tolerate soft errors in the NoC router control plane

    Chen, C. & Cotofana, SD., 2013, 26th Annual IEEE International SoC Conference). s.n. (ed.). Piscataway: IEEE Society, p. 374-379 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. A low-cost BRAM-Based function reuse for configurable soft-core processors in FPGAs

    Becker, P. H. E., Sartor, A. L., Brandalero, M., Trevisan Jost, T., Wong, S., Carro, L. & Beck, A. C., 2018, Applied Reconfigurable Computing: Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Proceedings. Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonpoulos, C. & Diniz, P. C. (eds.). Cham: Springer, p. 499-510 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10824 ).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. A low-cost, power-efficient texture cache architecture

    Antochi, I., Juurlink, BHH. & Cilio, AGM., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 250-257 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  93. A low-power carry skip adder with fast saturation

    Schulte, MJ., Chirca, K., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, 15th IEEE International conference on application-specific systems, architectures, and processors - ASAP 2004. Werner, B. (ed.). Piscataway: IEEE, p. 269-279 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. A low-power multithreaded processor for baseband communication systems

    Schulte, M., Glossner, CJ., Mamidi, S., Moudgill, M. & Vassiliadis, S., 2004, Computer systems: architectures, modeling, and simulation. Pimentel, AD. & Vassiliadis, S. (eds.). Berlin: Springer, p. 393-402 10 p. (Lecture Notes in Computer Science; vol. 3133).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. A low-power threshold logic family

    Padure, MD., Cotofana, SD., Vassiliadis, S., Dan, C. & Bodea, M., 2002, ICECS 2002; 9th IEEE International Conference on Electronica, Circuits and Systems. Piscatawy, NJ. USA: IEEE Society, p. 657-660 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. A mathematical game and its applications to the design of interconnection networks

    Yeh, CH. & Varvarigos, EA., 2001, Proceedings. Los Alamitos: IEEE, p. 21-30 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. A matrix-multiply unit for posits in reconfigurable logic leveraging (Open)CAPI

    Chen, J., Al-Ars, Z. & Hofstee, H. P., 2018, Proceedings of the Conference for Next Generation Arithmetic, CoNGA 2018. Association for Computing Machinery (ACM), p. 1-5 5 p. 1

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. A memcpy hardware accelarator solution for non cache-line aligned copies

    Campos Soares Borrego, F. & Wong, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 397-402 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. A memory-optimized bloom filter using an additional hashing function

    Ahmadi, M. & Wong, S., 2008, IEEE GLOBECOM 2008. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. A method to analyze the fault tolerance of molecular quantum-dot cellular automata systems

    Milosavljevic, D. & Cotofana, SD., 2006, Proceedings 2006 International Semiconductor conference. s.n. (ed.). Piscataway: IEEE Society, p. 399-402 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  101. A minimalistic for reconfigurable WFS-based immersive-audio

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, 2010 Intl. conf. on reconfigurable computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  102. A modified merging approach for datapath configuration time reduction

    Fazlali, M., 2010, Reconfigurable computing: architectures, tools and applications. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 318-328 11 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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