1. Article › Scientific › Peer-reviewed
  2. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  10. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  13. A nonlinear degradation path dependent end-of-life estimation framework from noisy observations

    Cucu Laurenciu, N. & Cotofana, SD., 2013, In : Microelectronics Reliability. 53, 9-11, p. 1213-1217 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. A novel productivity-driven logic element for field-programmable devices

    Marconi, T., Bertels, KLM. & Gaydadjiev, GN., 2014, In : International Journal of Electronics. 101, 6, p. 731-762 32 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. A software-defined communications baseband design

    Glossner, CJ., Iancu, D., Lu, J., Hokenck, E. & Moudgill, M., 2003, In : IEEE Communications Magazine. 41, 1, p. 4-12 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories

    van de Goor, AJ. & Tlili, IBS., 2003, In : IEEE Transactions on Computers. 52, 10, p. 1320-1330 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. A unified execution model for multiple computation models of streaming applications on a composable MPSoC

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, In : Journal of Systems Architecture. 59, 10, part C, p. 1032-1046 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

    Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 61-73 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Accelerating a geometrical approximated PCA algorithm using AVX2 and CUDA

    Machidon, A. L., Machidon, O. M., Ciobanu, C. B. & Ogrutan, P. L., 2020, In : Remote Sensing. 12, 12, p. 1-29 29 p., 1918.

    Research output: Contribution to journalArticleScientificpeer-review

  21. Active Resonator Reset in the Nonlinear Dispersive Regime of Circuit QED

    Bultink, C. C., Rol, M. A., O'Brien, T. E., Fu, X., Dikken, B. C. S., Dickel, C., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Schouten, R. N. & DiCarlo, L., 13 Sep 2016, In : Physical Review Applied. 6, 3, p. 1-10 034008.

    Research output: Contribution to journalArticleScientificpeer-review

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