1. Article › Scientific › Peer-reviewed
  2. Alternative architectures toward reliable memristive crossbar memories

    Vourkas, I., Stathis, D., Sirakoulis, G. C. & Hamdioui, S., 2016, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 1, p. 206-217 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set {2n+1,2n,2n-1},

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 8, p. 1500-1503 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. An analysis of limited wavelength translation in regular all-optical WDM networks

    Sharma, A. & Varvarigos, EA., 2001, In : Journal of Lightwave Technology. 18, 12, p. 1606-1619 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. An analysis of oblivious and adaptive routing in optical networks with wavelength translation

    Lang, JP., Sharma, A. & Varvarigos, EA., 2001, In : IEEE - ACM Transactions on Networking. 9, 4, p. 503-517 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. An industrial evaluation of DRAM tests

    van de Goor, AJ., 2004, In : IEEE Design & Test of Computers. 21, 5, p. 430-440 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Analog-to-digital converter based on single-electron tunneling transistors

    Hu, C., Cotofana, SD., Jiang, J. & Cai, Q., 2004, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12, 11, p. 1209-1213 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Analysis of RNAseq datasets from a comparative infectious disease zebrafish model using GeneTiles bioinformatics

    Veneman, WJ., de Sonneville, J., van der Kolk, KJ., Ordas, A., Al-Ars, Z., Meijer, AH. & Spaink, HP., 2015, In : Immunogenetics. 67, 3, p. 135-147 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices

    Wang, Y., Cotofana, SD. & Fang, L., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2521-2529 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Ant colony inspired microeconomic based resource management in ad hoc grids

    Abdullah, MT., Bertels, K. & Onana Alima, L., 2009, In : Lecture Notes in Computer Science. 5529, p. 189-198 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  13. Architectural support for 3D graphics in the complex streamed instruction set

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2002, In : International Journal of Parallel and Distributed Systems & Networks. 5, 4, p. 185-193 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Architecture enhancements for the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., de Sutter, B. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 66-81 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. Auction protocols for resource allocations in ad-hoc grids

    Pourebrahimi, B. & Bertels, KLM., 2008, In : Lecture Notes in Computer Science. LNCS5168, p. 520-533 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. Avoiding conversion and rearrangements overhead in SIMD architectures

    Shahbahrami, A., Juurlink, B., Borodin, D. & Vassiliadis, S., 2006, In : International Journal of Parallel Programming. 34, 3, p. 237-260 24 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. BRAM-LUT tradeoff on a polymorphic DES design

    Chaves Fernandes, R., Donchev, B., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 55-65 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Badwidth analysis of functional interconnects used as test access mechanism

    van den Berg, A., Ren, P., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2010, In : Journal of Electronic Testing: theory and applications. 26, 4, p. 453-464 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Brownian Circuits: Designs

    Lee, J., Peper, F., Cotofana, S., Naruse, M., Ohtsu, M., Kawazoe, T., Takahashi, Y., Shimokawa, T., Kish, L. B. & Kubota, T., 2016, In : International Journal of Unconventional Computing. 12, 5-6, p. 341-362 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. CCproc: a custom VLIW cryptography co-processor for symmetric-key ciphers

    Theodoropoulos, D., Siskos, A. & Pnevmatikatos, DN., 2009, In : Lecture Notes in Computer Science. 5453, p. 318-323 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

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