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  1. Article › Scientific › Peer-reviewed
  2. IEEE-Compliant IDCT on FPGA-augmented trimedia

    Sima, M., Cotofana, SD., van Eijndhoven, JTJ., Vassiliadis, S. & Vissers, K., 2005, In : Journal of V LSISignal Processing. 39, 3, p. 195-212 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

    Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Catthoor, F. & Cosemans, S., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 12, p. 3464-3472 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Impact and mitigation of SRAM read path aging

    Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Weckx, P., Cosemans, S., Catthoor, F. & Dehaene, W., 2018, In : Microelectronics Reliability. 87, p. 158-167 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Implementation of a streaming execution unit

    Cheresiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, HAG., 2003, In : Journal of Systems Architecture. 49, p. 599-617 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Implementing the 2-d wavelet transform on SIMD-enhanced general-purpose processors

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2008, In : IEEE Transactions on Multimedia. 10, 1, p. 43-51 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. In-memory database acceleration on FPGAs: a survey

    Fang, J., Mulder, Y. T. B., Hidders, J., Lee, J. & Hofstee, H. P., 2019, In : VLDB Journal.

    Research output: Contribution to journalArticleScientificpeer-review

  8. Influence of bit line coupling and twisting on the faulty behavior of DRAMs

    Al-Ars, Z., Hamdioui, S., van de Goor, AJ. & Al-Harbi, S., 2006, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 25, 12, p. 2989-2996 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Instruction-level fault tolerance configurability

    Borodin, D., Juurlink, B., Hamdioui, S. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

    Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Kükner, H., Weckx, P., Raghavan, P. & Catthoor, F., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1444-1454 11 p., 7819518.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Intelligent voltage ramp-up time adaptation for temperature noise reduction on memory-based PUF systems

    Cortez, AMMO., Hamdioui, S., Kaichouhi, A., van der Leest, V., Maes, R. & Schrijen, GJ., 2015, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 34, 7, p. 1162-1175 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Interprocedural compiler optimization for partial run-time reconfiguration

    Panainte, E., Bertels, K. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 161-172 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  13. Layout-based refined NPSF model for DRAM characterization and testing

    Sfikas, Y., Tsiatouhas, YE. & Hamdioui, S., 2014, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 6, p. 1446-1450 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Leakage-aware multiprocessor scheduling

    de Langen, PJ. & Juurlink, B., 2008, In : Journal of V LSISignal Processing. p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. Linked faults in random access memories: concept fault models, test algorithms, and industrial results

    Hamdioui, S., Al-Ars, Z., van de Goor, AJ. & Rodgers, M., 2004, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 23, 5, p. 737-757 21 p.

    Research output: Contribution to journalArticleScientificpeer-review

  16. Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

    Enachescu, M., Lefter, M., Voicu, G. & Cotofana, S., 2018, In : IEEE Transactions on Emerging Topics in Computing. 6, 2, p. 184-199 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures

    Lao, L., van Wee, B., Ashraf, I., van Someren, J., Khammassi, N., Bertels, K. & Almudever, C. G., 2019, In : Quantum Science and Technology. 4, 1, p. 1-20 20 p., 015005.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Memory and Communication Profiling for Accelerator-Based Platforms

    Ashraf, I., Khammassi, N., Taouil, M. & Bertels, K., 2018, In : IEEE Transactions on Computers. 67, 7, p. 934-948 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  19. Memory and storage management

    Campos Soares Borrego, F. & Wong, JSSM., 2010, In : IEEE Transactions on Computers. 59, 11, p. 1494-1507 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Memory fault modeling trends: a case study

    Hamdioui, S., Wadsworth, R. & delos Reyes, J., 2004, In : Journal of Electronic Testing: theory and applications. 20, p. 245-255 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  21. Memory test experiment: industrial results and data

    Hamdioui, S., van de Goor, AJ., Delos Reyes, J. & Rodgers, M., 2006, In : IEE Proceedings: Computers and Digital Techniques. 153, 1, p. 1-8 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

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