1. 3D/ 2.5D stacked IC cost modeling and test flow selection

    Hamdioui, S., 2014, p. 1-1. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  2. 64-bit floating-point FPGA matrix multiplication

    Dou, Y., Vassiliadis, S., Kuzmanov, GK. & Gaydadjiev, GN., 2005, Proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays (FPGA '05). s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 86-95 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. 7/3 and 7/2 Counters implemented in single electron technology

    Lageweg, CR., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings of ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 344-350 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. A 2D adressing mode for multimedia applications

    Kuzmanov, GK., Vassiliadis, S. & van Eijndhoven, JTJ., 2002, Embedded processor design challenges: Systems, Architectures, Modeling, and Simulation - SAMOS. Deprettere, EF., Teich, J. & Vassiliadis, S. (eds.). Berlin: Springer, p. 291-307 16 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

  5. A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

    Alavi, SM., Voicu, GR., Staszewski, RB., de Vreede, LCN. & Long, JR., 2013, Digest of Papers - 2013 IEEE Radio Frequency Integrated Circuits Symposium. Hancock, TM. (ed.). Piscataway, NJ, USA: IEEE Society, p. 167-170 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. A 3D stacked high performance scalable architecture for 3D fourier transform

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2012, 30th IEEE international conference on computer design. s.n. (ed.). New York: IEEE Society, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. A 3D-audio reconfigurable processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. A CMOS flip-flop featuring embedded threshold logic functions

    Padure, MD., Cotofana, SD. & Vassiliadis, S., 2002, Proceedings ProRISC 2002. Utrecht: Dutch Technology Foundation STW, p. 388-392 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. A CMOS semi-custom chip for mixed signal designs

    van Genderen, AJ., Cotofana, SD., de Graaf, G., Kaichouhi, A., Liedorp, J., Nouta, R., Pertijs, MAP. & Verhoeven, CJM., 2004, Proceedings of Pro-RISC 2004. Utrecht: Technology Foundation STW, p. 191-196 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. A Cache Architecture for Counting Bloom Filters: Theory and Application

    Ahmadi, M. & Wong, JSSM., 2011, In : Journal of Electrical and Computer Engineering. 2011, p. 1-10 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

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