1. 2001
  2. Performance of the complex streamed instruction set on image processing kernels

    Tcheressiz, D., Juurlink, BHH., Vassiliadis, S. & Wijshoff, H., 2001, Euro-Par 2001: proceedings. R Sakellariou & ... [et Al] (eds.). Berlin: Springer, p. 678-686 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Performance relevant issues for parallel computation models

    Juurlink, BHH. & Rieping, I., 2001, PDPTA'2001: proceedings. Vol 4. S.l.: CSREA, p. 1841-1847 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. RACE: A software-based fault tolerance scheme for systematically transforming ordinary algorithms to robust algorithms

    Yeh, C-H., Parhami, B., Varvarigos, EA. & Varvarigou, TA., 2001, Proceedings 15th international parallel and distributed processing symposium. Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Realistic fault models and test procedure for multi-port SRAMs

    Hamdioui, S., van de Goor, AJ., Eastwick, D. & Rodgers, M., 2001, Proceedings. Los Alamitos: IEEE, p. 65-72 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Reservation-based session routing for broadband communication networks with strict QoS requirements

    Yeh, CH., Varvarigos, EA., Bertsekas, D. & Mouftah, H., 2001, ICOIN the 15th: proceedings. Los Alamitos: IEEE, p. 593-600 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. SAD implementation in FPGA hardware

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 738-742 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Single electron encoded logic circuits

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, SAFE 2001: proceedings. Utrecht: STW Technology Foundation, p. 96-102 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Sparse matrix vector multiplication evaluation using the BBCS scheme

    Stathis, P., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 1. Y Manolopoulos & S Evripidou (eds.). S.l.: s.n., p. 40-49 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. Testing multi-port memories: theory and practice

    Hamdioui, S., 2001, S.l.: s.n.. 219 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  11. The MOLEN þµ-coded processor

    Vassiliadis, S., Wong, JSSM. & Cotofana, SD., 2001, Field-progammable logic and applications. G Goos & ... [et Al] (eds.). Berlin: Springer, p. 275-285

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientificpeer-review

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