1. 2001
  2. Transposition mechanism for sparse matrices on vector processors

    Stathis, P., Vassiliadis, S. & Cotofana, SD., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 641-645 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Variable length decoder implemented on a TriMedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 605-610 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. 2000
  5. A library of static and dynamic communication algorithms for parallel computation

    Varvarigos, EA., 2000, In : Telecommunication Systems: modeling, analysis, dssign and management. 13, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientific

  6. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. A taxonomy of custom computing machines

    Sima, M., Vassiliadis, S., Cotofana, SD., van Eijndhoven, JTJ. & Vissers, K., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 71-77 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  8. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. An experimental analysis of spot defects in SRAMs: realistic fault models and test

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Proceedings of the ninth Asian test symposium. DC Young (ed.). Piscataway: IEEE Society, p. 131-138 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Array based structure loop transformations for cache miss reduction

    Stanca, VM., Corporaal, H., Cotofana, SD. & Vassiliadis, S., 2000, Proceedings. MH Hamza (ed.). Annaheim: iASTED, p. 278-284 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  11. Array processor communication architecture with broadcast instructions

    Pechanek, GG., Vassiliadis, S., Glossner, CJ. & Larsen, LD., 2000, Priority date 26 Jul 2000

    Research output: PatentOther research output

  12. Automated design of an ASIP for image processing applications

    Schot, HJM. & Corporaal, H., 2000, In: A Bode, ...[et al.] (eds): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 1105-1109 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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