1. 2000
  2. BBCS based sparse matrix-vector multiplication: initial evaluation

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, Proceedings. M Deville & R Owens (eds.). New Brunswick: IMACS, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  3. Block based compression storage expected performance

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, HPC 2000: proceeding. NJ Dimopoulos & KF Li (eds.). S.l.: Kluwer Academic Publishers, p. 389-406 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Branch instruction processor and method

    Blaner, B., Jeremiah, TL., Vassiliadis, S. & Williams, PG., 2000, Priority date 19 May 1999

    Research output: Patent

  5. Compiler controlled dynamic scheduling of program instructions

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 23 Jun 1999

    Research output: Patent

  6. Complex streamed instructions: introduction and initial evaluation

    Vassiliadis, S., Juurlink, BHH. & Hakkennes, EA., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 400-408 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. Compounding preprocessor for cache

    Vassiliadis, S. & Blaner, B., 2000, Priority date 2 Feb 2000

    Research output: Patent

  8. Counter based superscalar instruction issuing

    Cotofana, SD., Juurlink, BHH. & Vassiliadis, S., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 307-315 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. Distributed processing array with component processors performing customized interpretation of instructions

    Pechanek, GG., Larsen, LD., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 3 Oct 2000

    Research output: Patent

  10. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  11. Embedded processor design using transport triggered architectures

    Corporaal, H., 2000, SPECLOG'2000 proceedings. R Creutzburg & K Egiazarian (eds.). Monistamo, Finland: TTKK, p. 469-469

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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