1. 2000
  2. Multi-cost routing in Max-Min fair share networks

    Gutierrez, FJ., Varvarigos, EA. & Vassiliadis, S., 2000, Proceedings. Vol. 2. S.l.: s.n., p. 1294-1304 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  3. Multilayer VLSI layout for interconnection networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, ICPP 2000 proceedings. DJ Lilja (ed.). Los Alamitos: IEEE, p. 33-40 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. Multimedia enhanced general-purpose processors

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ICME 2000: latest advances in the fast changing world of multimedia. Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  5. Multimedia execution hardware accelerator

    Hakkennes, EA. & Vassiliadis, S., 2000, In : Journal of V LSISignal Processing. 28, 3, p. 221-234 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Multiple machine view execution in computer system

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 20 Jun 2000

    Research output: Patent

  7. Novel concept of a multistatic antenna configuration enhances high range resolution FMCW radar with instantaneous angular resolution capability

    Swart, PJF., Muller, FL. & Ligthart, LP., 2000, ISAP 2000 proceedings Vol. 1. Tokyo: IEICE, p. 185-188 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Optimal broadcast on parallel locality models

    Juurlink, BHH., Kolman, P., Meyer Auf Der Heide, F. & Rieping, I., 2000, SIROCCO 7: proceedings in informatics 7. M Flammini (ed.). S.l.: Carleton Scientific, p. 211-225 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. Optimal-depth circuits for prefex computation and addition

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, Proceedings. MB Matthews (ed.). Piscataway: IEEE Society, p. 1349-1353 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Parallel computer architecture

    Müller, S., Stenström, P., Valero, M. & Vassiliadis, S., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 537-538 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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