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  1. Using a CISC microcontroller to test embedded memories

    van de Goor, AJ., Hamdioui, S. & Gaydadjiev, GN., 2010, IEEE intl. symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 382-387 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  2. Using a Polymorphic VLIW Processor to Improve Schedulability and Performance for Mixed-criticality Systems

    Hoozemans, J., van Straten, J. & Wong, S., Aug 2017, 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Danvers: IEEE, p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Using linear tests for transient faults in DRAMs

    Al-Ars, Z., Hamdioui, S. & Gaydadjiev, GN., 2006, International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. -

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

    Mariani, GS., Sima, VM., Palermo, G., Zaccaria, V., Silvano, C. & Bertels, KLM., 2012, Design, automation & test in Europe conference & exhibition. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Using wavelet transform self-similarity for effective multiple description video coding

    Choupani, R., Wong, S. & Tolun, M., 2016, 10th International Conference on Information, Communications and Signal Processing, ICICS 2015. Piscataway, NJ: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. VASILE: a reconfigurable vector architecture for instruction level frequency scaling

    Petrica, L., Codreanu, V. & Cotofana, SD., 2013, 12th IEEE low voltage low power conference. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications

    Hoozemans, J., Heij, R., van Straten, J. & Al-Ars, Z., 2017, Applied Reconfigurable Computing: 13th International Symposium, ARC 2017. Wong, S., Beck, A. C., Bertels, K. & Carro, L. (eds.). Cham: Springer, p. 36-43 8 p. (Lecture Notes in Computer Science; vol. 10216)(Theoretical Computer Science and General Issues; vol. 10216).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. VLSI layout and packaging of butterfly networks

    Yeh, CH., Parhami, B., Varvarigos, EA. & Lee, H., 2000, SPAA 2000. New York: Association for Computing Machinery (ACM), p. 196-205 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  9. Variability and reliability analyses in SRAM decoder

    Seyab, MSK. & Hamdioui, S., 2013, 4th Workshop on design for reliability. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Variable length decoder implemented on a TriMedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 605-610 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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