1. Article › Scientific › Peer-reviewed
  2. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. A hardware/software platform for QoS bridging over multi-chip NoC-based systems

    Beyranvand Nejad, A., Molnos, AM., Escudero Martinez, M. & Goossens, KGW., 2013, In : Parallel Computing. 39, 9, p. 424-441 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. A low-power multithreaded processor for software defined radio

    Schulte, M., Glossner, CJ., Jinturkar, S., Moudgill, M. & Vassiliadis, S., 2006, In : Journal of V LSISignal Processing. 43, 2-3, p. 143-159 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  10. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. A multithreaded processor architecture for SDR

    Glossner, CJ., Raja, T., Hokenek, E. & Moudgill, M., 2002, In : Proceedings of the Korean Institute of Communication Sciences. 19, 11, p. 70-85 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

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