51 - 60 out of 1,541Page size: 10
  1. 2019

  2. Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow

    Peltenburg, J., van Straten, J., Brobbel, M., Hofstee, H. P. & Al-Ars, Z., 2019, Applied Reconfigurable Computing: 15th International Symposium, ARC 2019, Proceedings. Hochberger, C., Koch, A., Diniz, P., Woods, R. & Nelson, B. (eds.). Cham: Springer Nature, p. 32-47 16 p. (Lecture Notes in Computer Science; vol. 11444 LNCS).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  3. Time-division Multiplexing Automata Processor

    Yu, J., Du Nguyen, H. A., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) : Proceedings. IEEE, p. 794-799 6 p. 8715140

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  4. Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V

    Fritzmann, T., Sharif, U., Müller-Gritschneder, D., Reinbrecht, C., Schlichtmann, U. & Sepulveda, J., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings . IEEE, p. 1148-1153 6 p. 8715173

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  5. eQASM: An executable quantum instruction set architecture

    Fu, X., Riesebos, L., Rol, M. A., Van Straten, J., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., Newsum, V., Loh, K. K. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., Dicarlo, L. & Bertels, K., 2019, Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. Louri, A. & Venkataramani, G. P. (eds.). Piscataway, NJ: IEEE, p. 224-237 14 p. 8675197

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  6. 2018

  7. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  8. Complementary arranged graphene nanoribbon-based boolean gates

    Jiang, Y., Laurenciu, N. C. & Cotofana, S., 17 Jul 2018, Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018. Cotofana, S. & Sirakoulis, G. C. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 51-57 7 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  9. Understanding MPSoCs: Exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs

    Sepulveda, J., Reinbrecht, C., Azad, S. P., Niazmand, B. & Jervan, G., 15 Jul 2018, Proceedings - 2018 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2018. Mudge, T. & Pnevmatikatos, D. N. (eds.). New York: Association for Computing Machinery (ACM), p. 162-166 5 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  10. Device aging: A reliability and security concern

    Kraak, D., Taouil, M., Hamdioui, S., Weckx, P., Catthoor, F., Chatterjee, A., Singh, A., Wunderlich, H. & Karimi, N., 1 May 2018, 2018 IEEE 23rd European Test Symposium (ETS). p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  11. Degradation analysis of high performance 14nm FinFET SRAM

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 1 Mar 2018, 2018 Design, Automation Test in Europe Conference Exhibition (DATE). p. 201-206 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review

  12. A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S. & Bertels, K., 2018, In : IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 37, 2, p. 311-323 13 p.

    Research output: Contribution to journal › Article › Scientific › peer-review

Previous 12 3 4 5 6 7 8 9 ...155 Next

ID: 19943