1. 2017
  2. An experimental microarchitecture for a superconducting qantum processor

    Fu, X., Rol, M. A., Bultink, C. C., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., DiCarlo, L. & Bertels, K., 14 Oct 2017, MICRO 2017 - 50th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings. IEEE Computer Society, Vol. Part F131207. p. 813-825 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Memristive devices for computing: Beyond CMOS and beyond von Neumann

    Du Nguyen, H. A., Yu, J., Xie, L., Taouil, M., Hamdioui, S. & Fey, D., Oct 2017, 25th IFIP/IEEE International Conference on Very Large Scale Integration.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. Using a Polymorphic VLIW Processor to Improve Schedulability and Performance for Mixed-criticality Systems

    Hoozemans, J., van Straten, J. & Wong, S., Aug 2017, 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Danvers: IEEE, p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Restless Tuneup of High-Fidelity Qubit Gates

    Rol, M. A., Bultink, C. C., O'Brien, T. E., De Jong, S. R., Theis, L. S., Fu, X., Luthi, F., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Deurloo, D., Schouten, R. N., Wilhelm, F. K. & Dicarlo, L., 24 Apr 2017, In : Physical Review Applied. 7, 4, 041001.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Improved Dynamic Cache Sharing for Communicating Threads on a Runtime-Adaptable Processor

    Hoozemans, J., Lorenzon, A., Schneider Beck, A. C. & Wong, S., Jan 2017, p. 1-9. 9 p.

    Research output: Contribution to conferenceAbstractScientific

  7. A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons

    Yu, J., Hogervorst, T. & Nane, R., 2017, GLSVLSI '17 Proceedings of the on Great Lakes Symposium on VLSI 2017 . New York: Association for Computing Machinery (ACM), p. 71-76 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. An experience with Chalcogenide memristors, and implications on memory and computer applications

    Escudero-López, M., Amat, E., Rubio, A. & Pouyan, P., 2017, 2016 Conference on Design of Circuits and Integrated Systems (DCIS). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Patent No. US 9,824,753, Priority date 21 Oct 2015

    Research output: PatentOther research output

  11. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Priority date 21 Oct 2015, Priority No. US 2017/0117041

    Research output: PatentOther research output

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