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  2. Comparing Neural Network Based Decoders for the Surface Code

    Varsamopoulos, S., Bertels, K. & Almudever, C. G., 1 Feb 2020, In : IEEE Transactions on Computers. 69, 2, p. 300-311 12 p., 8880492.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates

    Kukner, H., Khan, F., Weckx, P., Raghavan, P., Hamdioui, S., Kaczer, B., Catthoor, F., van der Perre, L., Lauwereins, R. & Groeseneken, G., 2014, In : IEEE Transactions on Device and Materials Reliability. 14, 1, p. 182-193 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Compositional, dynamic cach management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD., Heijligers, MJM. & van Eijndhoven, JTJ., 2009, In : Journal of Signal Processing Systems: the journal of DSPtechnologies. 57, 2

    Research output: Contribution to journalArticleScientificpeer-review

  5. Computing division using single-electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : IEEE Transactions on Nanotechnology. 6, 4, p. 451-459 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Context aware slope based transistor-level aging model

    Cucu Laurenciu, N. & Cotofana, SD., 2012, In : Microelectronics Reliability. 52, 9-10, p. 1-6 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Controlled degradation stochastic resonance in adaptive averaging cell based architectures

    Aymerich, N., Cotofana, SD. & Rubio, A., 2013, In : IEEE Transactions on Nanotechnology. 12, 6, p. 888-896 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  8. Controlling a complete hardware synthesis toolchain with LARA aspects

    Cardoso, JMP., Carvalho, T., Coutinho, JGF., Nobre, R., Nane, R., Diniz, P., Petrov, Z., Luk, W. & Bertels, KLM., 2013, In : Microprocessors and Microsystems. 37, 8, p. 1073-1089 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Cost-efficient SHA hardware accelerators

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 999-1008 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. Critical transistors nexus based circuit-level aging assessment and prediction

    Cucu Laurenciu, N. & Cotofana, SD., 2014, In : Journal of Parallel and Distributed Computing. 74, 6, p. 2512-2520 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Cross-layer designs architecture for LEO satellite ad hoc network

    Chang, Z. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. 5031, p. 164-176 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

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