1. 2019
  2. Software-Based Mitigation for Memory Address Decoder Aging

    Kraak, D., Gursoy, C. C., Agbo, I. O., Taouil, M., Jenihhin, M., Raik, J. & Hamdioui, S., 2019, 2019 IEEE Latin American Test Symposium (LATS). Danvers: IEEE, p. 1-6 6 p. 8704595

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. SparkGA2: Production-quality memory-efficient Apache Spark based genome analysis framework

    Mushtaq, H., Ahmed, N. & Al-Ars, Z., 2019, In : PLoS ONE. 14, 12, p. 1-14 14 p., e0224784.

    Research output: Contribution to journalArticleScientificpeer-review

  4. SparkJNI: A Toolchain for Hardware Accelerated Big Data Apache Spark

    Voicu, T. A. & Al-Ars, Z., 2019, 2019 4th IEEE International Conference on Big Data Analytics, ICBDA 2019. Guan, S-U., Zhang, K. & Cao, J. (eds.). Piscataway, NJ, USA: IEEE, p. 152-157 6 p. 8713201

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  5. Sparstition: A partitioning scheme for large-scale sparse matrix vector multiplication on FPGA

    Sigurbergsson, B., Hogervorst, T., Qiu, T. D. & Nane, R., 2019, 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP): Proceedings. IEEE, p. 51-58 8 p. 8825125

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow

    Peltenburg, J., van Straten, J., Brobbel, M., Hofstee, H. P. & Al-Ars, Z., 2019, Applied Reconfigurable Computing: 15th International Symposium, ARC 2019, Proceedings. Hochberger, C., Koch, A., Diniz, P., Woods, R. & Nelson, B. (eds.). Cham: Springer, p. 32-47 16 p. (Lecture Notes in Computer Science; vol. 11444 LNCS).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Time-division Multiplexing Automata Processor

    Yu, J., Du Nguyen, H. A., Abu Lebdeh, M., Taouil, M. & Hamdioui, S., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) : Proceedings. IEEE, p. 794-799 6 p. 8715140

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V

    Fritzmann, T., Sharif, U., Müller-Gritschneder, D., Reinbrecht, C., Schlichtmann, U. & Sepulveda, J., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings . IEEE, p. 1148-1153 6 p. 8715173

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Untestable faults identification in GPGPUs for safety-critical applications

    Condia, J. E. R., Da Silva, F. A., Hamdioui, S., Sauer, C. & Reorda, M. S., 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers (IEEE), p. 570-573 4 p. 8964677

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. eQASM: An executable quantum instruction set architecture

    Fu, X., Riesebos, L., Rol, M. A., Van Straten, J., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., Newsum, V., Loh, K. K. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., Dicarlo, L. & Bertels, K., 2019, Proceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019. Louri, A. & Venkataramani, G. P. (eds.). Piscataway, NJ: IEEE, p. 224-237 14 p. 8675197

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. 2018
  12. A High-Bandwidth Snappy Decompressor in Reconfigurable Logic

    Fang, J., Chen, J., Al-Ars, Z., Hofstee, P. & Hidders, J., 30 Sep 2018, 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS). IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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