1. 2000
  2. A look inside the learning process of neural networks

    Bertels, KLM., Neuberg, L., Vassiliadis, S. & Pechanek, GG., 2000, In : Complexity. 5, 6, p. 34-38 5 p.

    Research output: Contribution to journalArticleScientificpeer-review

  3. A taxonomy of custom computing machines

    Sima, M., Vassiliadis, S., Cotofana, SD., van Eijndhoven, JTJ. & Vissers, K., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 71-77 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  4. A virtual circuit deflection protocol

    Varvarigos, EA. & Lang, JP., 2000, In : IEEE - ACM Transactions on Networking. 7, 3, p. 335-349 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. An experimental analysis of spot defects in SRAMs: realistic fault models and test

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Proceedings of the ninth Asian test symposium. DC Young (ed.). Piscataway: IEEE Society, p. 131-138 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Array based structure loop transformations for cache miss reduction

    Stanca, VM., Corporaal, H., Cotofana, SD. & Vassiliadis, S., 2000, Proceedings. MH Hamza (ed.). Annaheim: iASTED, p. 278-284 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  7. Array processor communication architecture with broadcast instructions

    Pechanek, GG., Vassiliadis, S., Glossner, CJ. & Larsen, LD., 2000, Priority date 26 Jul 2000

    Research output: Patent

  8. Automated design of an ASIP for image processing applications

    Schot, HJM. & Corporaal, H., 2000, In: A Bode, ...[et al.] (eds): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 1105-1109 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  9. Automatic SIMD parallelization of embedded applications based on pattern recognition

    Manniesing, R., Karkowski, I. & Corporaal, H., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 349-356 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  10. BBCS based sparse matrix-vector multiplication: initial evaluation

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, Proceedings. M Deville & R Owens (eds.). New Brunswick: IMACS, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  11. Block based compression storage expected performance

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 2000, HPC 2000: proceeding. NJ Dimopoulos & KF Li (eds.). S.l.: Kluwer Academic Publishers, p. 389-406 18 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. Branch instruction processor and method

    Blaner, B., Jeremiah, TL., Vassiliadis, S. & Williams, PG., 2000, Priority date 19 May 1999

    Research output: Patent

  13. Compiler controlled dynamic scheduling of program instructions

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 23 Jun 1999

    Research output: Patent

  14. Complex streamed instructions: introduction and initial evaluation

    Vassiliadis, S., Juurlink, BHH. & Hakkennes, EA., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 400-408 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. Compounding preprocessor for cache

    Vassiliadis, S. & Blaner, B., 2000, Priority date 2 Feb 2000

    Research output: Patent

  16. Counter based superscalar instruction issuing

    Cotofana, SD., Juurlink, BHH. & Vassiliadis, S., 2000, Proceedings, vol. 1. Los Alamitos: IEEE, p. 307-315 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  17. Distributed processing array with component processors performing customized interpretation of instructions

    Pechanek, GG., Larsen, LD., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 3 Oct 2000

    Research output: Patent

  18. Elementary function generators for neural-network emulators

    Vassiliadis, S., Zhang, M. & Delgado-Frias, JG., 2000, In : IEEE Transactions on Neural Networks. 11, 6, p. 1438-1449 12 p.

    Research output: Contribution to journalArticleScientific

  19. Embedded processor design using transport triggered architectures

    Corporaal, H., 2000, SPECLOG'2000 proceedings. R Creutzburg & K Egiazarian (eds.). Monistamo, Finland: TTKK, p. 469-469

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  20. Garbage collection for the Delft Java Processor

    Berlea, A., Cotofana, SD., Athanasiu, I., Glossner, CJ. & Vassiliadis, S., 2000, Proceedings. MH Hamza (ed.). Annaheim: iASTED, p. 232-238 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  21. General-purpose Huffman encoding extension

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ITCC 2000. Los Alamitos: IEEE, p. 158-163 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  22. Hashed addressed caches for embedded pointer based codes

    Stanca, VM., Vassiliadis, S., Cotofana, SD. & Corporaal, H., 2000, In: A Bode, ...(et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 956-968 13 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  23. Hierarchical approach for hardware/software systems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 2000, CAS 2000 proceedings. Vol. 1. 2000 international semicondutor conference 23rd edition. D Dascalu (ed.). Piscataway: IEEE Society, p. 223-226 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. Hierarchical interfaces for hardware/software systems

    Niculiu, T., Aktouf, C. & Cotofana, SD., 2000, 14th European simulation multiconference. D Landeghem, V. (ed.). San Diego: Society for Computer Simulation International, p. 647-654 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  25. JAVA signal processing: FFTs with bitecodes

    Glossner, CJ., Thilo, J. & Vassiliadis, S., 2000, In : Concurrency: Practice and Experience. 10, 11-13, p. 1173-1178 6 p.

    Research output: Contribution to journalArticleScientific

  26. Link-time effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 2000, In : Future Generation Computer Systems: the international journal of grid computing: theory, methods and applications. 16, p. 503-511 9 p.

    Research output: Contribution to journalArticleScientific

  27. March tests for realistic faults in two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Records of the 2000 IEEE international workshop on memory technology, design and testing. R Rajsuman & T Wik (eds.). Los Alamitos: IEEE, p. 73-78 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  28. Massively parallel multiple-folded clustered processor mesh array

    Pechanek, GG., Vassiliadis, S. & Delgado-Frias, JG., 2000, Priority date 21 Mar 2000

    Research output: Patent

  29. Multi-cost routing in Max-Min fair share networks

    Gutierrez, FJ., Varvarigos, EA. & Vassiliadis, S., 2000, Proceedings. Vol. 2. S.l.: s.n., p. 1294-1304 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  30. Multilayer VLSI layout for interconnection networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, ICPP 2000 proceedings. DJ Lilja (ed.). Los Alamitos: IEEE, p. 33-40 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  31. Multimedia enhanced general-purpose processors

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ICME 2000: latest advances in the fast changing world of multimedia. Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  32. Multimedia execution hardware accelerator

    Hakkennes, EA. & Vassiliadis, S., 2000, In : Journal of V LSISignal Processing. 28, 3, p. 221-234 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. Multiple machine view execution in computer system

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 20 Jun 2000

    Research output: Patent

  34. Novel concept of a multistatic antenna configuration enhances high range resolution FMCW radar with instantaneous angular resolution capability

    Swart, PJF., Muller, FL. & Ligthart, LP., 2000, ISAP 2000 proceedings Vol. 1. Tokyo: IEICE, p. 185-188 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Optimal broadcast on parallel locality models

    Juurlink, BHH., Kolman, P., Meyer Auf Der Heide, F. & Rieping, I., 2000, SIROCCO 7: proceedings in informatics 7. M Flammini (ed.). S.l.: Carleton Scientific, p. 211-225 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  36. Optimal-depth circuits for prefex computation and addition

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, Proceedings. MB Matthews (ed.). Piscataway: IEEE Society, p. 1349-1353 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  37. Parallel computer architecture

    Müller, S., Stenström, P., Valero, M. & Vassiliadis, S., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 537-538 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  38. Routing and embeddings in super Cayley graphs

    Yeh, CH., Varvarigos, EA. & Lee, H., 2000, V Malyshkin (eds.): Parallel computing technologies [Lecture notes in computer science 1662]. Berlin: Springer, p. 151-165 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  39. Scalable communication protocols for high-speed networks

    Yeh, CH., Varvarigos, EA., Parhami, B. & Sharma, V., 2000, Proceedings. Annaheim: iASTED, p. 1-7 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  40. Signed digit addition and related operations with threshold logic

    Cotofana, SD. & Vassiliadis, S., 2000, In : IEEE Transactions on Computers. 49, 3, p. 193-207 15 p.

    Research output: Contribution to journalArticleScientific

  41. System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction

    Vassiliadis, S., Blaner, B. & Jeremiah, TL., 2000, Priority date 28 Jun 2000

    Research output: Patent

  42. Test point insertion for compact test sets

    Geuzebroek, MJ., van Linden, JT. & van de Goor Ph D, AJ., 2000, International tests conference 2000: proceedings. Los Alamitos: IEEE, p. 292-301 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, In : Journal of Electronic Testing: theory and applications. 16, 5, p. 487-498 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  44. The -Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, In : Journal of Lightwave Technology. 18, 8, p. 1049-1063 15 p.

    Research output: Contribution to journalArticleScientific

  45. The Artemis architecture workbench

    Pimentel, AD., van der Wolf, P., Deprettere, EFA., Hertzberger, LO., van Eijndhoven, JTJ. & Vassiliadis, S., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 53-62 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  46. The ManArray embedded processor architecture

    Pechanek, GG. & Vassiliadis, S., 2000, Proceedings, vol. 1. F Vajda (ed.). Los Alamitos: IEEE, p. 348-355 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  47. The impact of code positioning on ILP scheduling

    Cilio, AGM. & Corporaal, H., 2000, ASCI 2000 proceedings. LJ Vliet, V. (ed.). Delft: Advanced School for Computing and Imaging, p. 37-44 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  48. The lambda-Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, Proceedings thirty-seventh annual Allerton conference on communication, control and computing. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  49. The scalable networking scheme for high-speed networks

    Yeh, CH. & Varvarigos, EA., 2000, ICC 2000 conference record: global convergence through communications. Piscataway: IEEE Society, p. 1335-1342 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  50. VLSI layout and packaging of butterfly networks

    Yeh, CH., Parhami, B., Varvarigos, EA. & Lee, H., 2000, SPAA 2000. New York: Association for Computing Machinery (ACM), p. 196-205 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  51. 1999
  52. 2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE, p. 436-440 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  53. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  55. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. Agent based social simulation in markets

    Bertels, KLM. & Boman, M., 1999, WAEC'99: proceedings. Yiming Ye & Jiming Liu (eds.). S.l.: s.n., p. 1-9 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  57. Algorithm development for scalable processor systems based on transport triggered architectures

    Corporaal, H., 1999, Proceedings. AB Smolders & MP Haarlem, V. (eds.). Dwingeloo: ASTRON, p. 225-234 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  58. Capacitive threshold logic: a designer perspective

    Padure, MD., Dan, C., Cotofana, SD., Bodea, M. & Vassiliadis, S., 1999, CAS '99 proceedings. Vol. 1. S.l.: IEEE Society, p. 81-84 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. Computer architectuur, implementatie en realisatie

    Corporaal, H., 1999, ICT-zakboekje. TMA Bemelmans, PME Bra, D., M Looijen & G Oortmerssen, V. (eds.). Arnhem: Koninklijke PBNA, p. 569-663

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterProfessional

  60. Delft-Java dynamic translation

    Glossner, CJ. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 57-61 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  61. Efficient VLSI layouts of hypercubic networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 98-105 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  62. Evaluation of a potential for automatic SIMD parallelization of embedded applications

    Manniesing, R., Karkowski, I. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 103-110 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Eighth Asian Test Symposium: proceedings. Los Alamitos: IEEE, p. 185-191 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. Floating point to fixed point conversion of C code

    Cilio, AGM. & Corporaal, H., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 229-243 15 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. Global program optimization: register allocation of static scalar objects

    Cilio, AGM. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 52-57 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. Hardwired Paeth codec for portable network graphics (PNG)

    Hakkennes, EA. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 318-325 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. Hierarchical mixed simulation for intelligent interfaces of microsystems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 1999, CAS '99 proceedings. Vol. 2. S.l.: IEEE Society, p. 515-518 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Illegal state space identification for sequential circuit test generation

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Proceedings. D Borrione & R Ernst (eds.). Los Alamitos: IEEE, p. 741-746 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. Instruction set synthesis using operation pattern detection

    Arnold, M. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 413-420 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  70. ManArray processor interconnection network: an introduction

    Pechanek, GG., Vassiliadis, S. & Pitsianis, N., 1999, Euro-Par '99 Parallel Processing: proceedings (Lecture notes in computer science 1685). P Amestoy (ed.). Berlin: Springer, p. 761-765 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  71. March tests for word-oriented two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 1999, Eighth Asian Test Symposium: proceedings. Los Alamitos: IEEE, p. 53-60 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. Multimedia hardware accelerators

    Hakkennes, EA., 1999, S.l.: s.n.. 140 p.

    Research output: ThesisDissertation (TU Delft)

  73. Multistatic FMCW radar for collision avoidance applications, optimization of the antenna configuration and improvement of the data processing

    Steenstra, HT., Muller, FL. & Swart, PJF., 1999, MIOP 99: conference proceedings.Vol. 2.. Portsmouth: Microwave Engineering Europe, p. 13-16 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  74. Network routing algorithms

    Varvarigos, EA. & Yeh, CH., 1999, Wiley encyclopedia of electrical and electronics engineering. New York: Wiley, p. 218-226

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  75. Parallel algorithms on the rotation-exchange network - a trivalent variant of the star graph

    Yeh, CH. & Varvarigos, EA., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 303-309 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  76. Port interference faults in two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 1999, Proceedings. S.l.: IEEE Society, p. 1001-1010 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. Qualitative company performance evaluation: linear discriminant analysis and neural network models

    Bertels, KLM., Jacques, JM., Neuberg, L. & Gatot, L., 1999, In : European Journal of Operational Research. 115, 3, p. 608-615 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  78. Remove: a computer architecture designed for modern VLSI technology

    Roos, S., Lamberts, R. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 421-428 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Serial binary multiplication with feed-forward neural networks

    Cotofana, SD. & Vassiliadis, S., 1999, In : Neurocomputing. 28, p. 1-19 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  80. Superscalar branch instruction processor

    Jeremiah, TL., Vassiliadis, S. & Blaner, B., 1999, CSCS-12: proceedings. Vol. 2. I Dumitrache & M Dobre (eds.). Bucharest: Editura Politehnica, p. 163-168 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. TTAs: missing the ILP complexity wall

    Corporaal, H., 1999, In : Journal of Systems Architecture. 45, p. 949-973 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  82. Testability of the Philips 80C51 micro-controller

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Proceedings. S.l.: IEEE Society, p. 820-829 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. The Paderborn University BSP (PUB) library design, implementation and performance

    Bonorden, O., Juurlink, BHH., von Otte, I. & Rieping, I., 1999, Proceedings of the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. B Werner (ed.). Los Alamitos: IEEE, p. 99-104 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. The \-scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 1999, Proceedings. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  85. The effect of process switches on branch prediction accuracy

    Kisuki, T., Corporaal, H. & Knijnenburg, PMW., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 81-88 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  86. The priority broadcast scheme for dynamic broadcast in hypercubes and related networks

    Yeh, CH., Varvarigos, EA. & Lee, H., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 294-301 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  87. The recursive grid layout scheme for VLSI layout of hierarchical networks

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999 Proceedings. Los Alamitos: IEEE, p. 441-445 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  88. Towards the additional use of phase processing in multistatic FMCW radar, considerations and experimental results

    Swart, PJF., Steenstra, HT., Muller, FL., van der Zwan, WF., van Genderen, P., Ligthart, LP., Reijns, GL. & van Gemund, AJC., 1999, Conference proceedings. Vol. 1. London: Microwave Engineering Europe, p. 238-241 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Transforming and parallelizing ANSI C programs using pattern recognition

    Boekhold, M., Karkowski, I. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 673-682 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  90. Vector ISA extension for sparse matrix-vector multiplication

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 1999, Euro-Par '99 Parallel Processing: proceedings (Lecture notes in computer science 1685). P Amestoy (ed.). Berlin: Springer, p. 708-715 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  91. 1998
  92. Application of Transient Heat Flux Sensors to Resolve Time-Dependent Convective Heat Transfer from Wall-mounted Cubes

    Meinders, ER., Geuzebroek, MJ., Hanjalic, K. & Ortega, A., 1998, ASME Conference. Nelson, RA., Chopin, T. & Thynell, ST. (eds.). p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

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