1. 2000
  2. Multilayer VLSI layout for interconnection networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, ICPP 2000 proceedings. DJ Lilja (ed.). Los Alamitos: IEEE, p. 33-40 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  3. Multimedia enhanced general-purpose processors

    Wong, JSSM., Cotofana, SD. & Vassiliadis, S., 2000, ICME 2000: latest advances in the fast changing world of multimedia. Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  4. Multimedia execution hardware accelerator

    Hakkennes, EA. & Vassiliadis, S., 2000, In : Journal of V LSISignal Processing. 28, 3, p. 221-234 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Multiple machine view execution in computer system

    D'Arcy, PG., Jinturkar, S., Glossner, CJ. & Vassiliadis, S., 2000, Priority date 20 Jun 2000

    Research output: PatentOther research output

  6. Novel concept of a multistatic antenna configuration enhances high range resolution FMCW radar with instantaneous angular resolution capability

    Swart, PJF., Muller, FL. & Ligthart, LP., 2000, ISAP 2000 proceedings Vol. 1. Tokyo: IEICE, p. 185-188 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. Optimal broadcast on parallel locality models

    Juurlink, BHH., Kolman, P., Meyer Auf Der Heide, F. & Rieping, I., 2000, SIROCCO 7: proceedings in informatics 7. M Flammini (ed.). S.l.: Carleton Scientific, p. 211-225 15 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  8. Optimal-depth circuits for prefex computation and addition

    Yeh, CH., Varvarigos, EA. & Parhami, B., 2000, Proceedings. MB Matthews (ed.). Piscataway: IEEE Society, p. 1349-1353 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. Parallel computer architecture

    Müller, S., Stenström, P., Valero, M. & Vassiliadis, S., 2000, In: A Bode, ...[et al.] (eds.): Euro-Par 2000 parallel processing [Lecture notes in computer science 1900]. Berlin: Springer, p. 537-538 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  10. Routing and embeddings in super Cayley graphs

    Yeh, CH., Varvarigos, EA. & Lee, H., 2000, V Malyshkin (eds.): Parallel computing technologies [Lecture notes in computer science 1662]. Berlin: Springer, p. 151-165 15 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  11. Scalable communication protocols for high-speed networks

    Yeh, CH., Varvarigos, EA., Parhami, B. & Sharma, V., 2000, Proceedings. Annaheim: iASTED, p. 1-7 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  12. Signed digit addition and related operations with threshold logic

    Cotofana, SD. & Vassiliadis, S., 2000, In : IEEE Transactions on Computers. 49, 3, p. 193-207 15 p.

    Research output: Contribution to journalArticleScientific

  13. System for preparing instructions for instruction parallel processor and system with mechanism for branching in the middle of a compound instruction

    Vassiliadis, S., Blaner, B. & Jeremiah, TL., 2000, Priority date 28 Jun 2000

    Research output: PatentOther research output

  14. System for preparing instructions for instruction parrellel processor and system with mechanism for branching in the middle of a compound instruction

    Vassiliadis, S., Blaner, B. & Jeremiah, TL., 2000, Priority date 25 Feb 1998

    Research output: PatentOther research output

  15. System for preparing instructions for instruction parrellel processor and system with mechanism for branching in the middle of a compound instruction

    Vassiliadis, S., Blaner, B. & Jeremiah, TL., 2000, Priority date 29 Apr 1998

    Research output: PatentOther research output

  16. Test point insertion for compact test sets

    Geuzebroek, MJ., van Linden, JT. & van de Goor Ph D, AJ., 2000, International tests conference 2000: proceedings. Los Alamitos: IEEE, p. 292-301 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, In : Journal of Electronic Testing: theory and applications. 16, 5, p. 487-498 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. The -Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, In : Journal of Lightwave Technology. 18, 8, p. 1049-1063 15 p.

    Research output: Contribution to journalArticleScientific

  19. The Artemis architecture workbench

    Pimentel, AD., van der Wolf, P., Deprettere, EFA., Hertzberger, LO., van Eijndhoven, JTJ. & Vassiliadis, S., 2000, Proceedings. JP Veen (ed.). Utrecht: STW Technology Foundation, p. 53-62 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  20. The ManArray embedded processor architecture

    Pechanek, GG. & Vassiliadis, S., 2000, Proceedings, vol. 1. F Vajda (ed.). Los Alamitos: IEEE, p. 348-355 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  21. The impact of code positioning on ILP scheduling

    Cilio, AGM. & Corporaal, H., 2000, ASCI 2000 proceedings. LJ Vliet, V. (ed.). Delft: Advanced School for Computing and Imaging, p. 37-44 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  22. The lambda-Scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 2000, Proceedings thirty-seventh annual Allerton conference on communication, control and computing. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  23. The scalable networking scheme for high-speed networks

    Yeh, CH. & Varvarigos, EA., 2000, ICC 2000 conference record: global convergence through communications. Piscataway: IEEE Society, p. 1335-1342 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  24. VLSI layout and packaging of butterfly networks

    Yeh, CH., Parhami, B., Varvarigos, EA. & Lee, H., 2000, SPAA 2000. New York: Association for Computing Machinery (ACM), p. 196-205 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  25. 1999
  26. 2.5n-Step sorting on nxn meshes in the presence of 0(Vn) worst-case faults

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999. Los Alamitos: IEEE, p. 436-440 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  27. A linker for effective whole-program optimizations

    Cilio, AGM. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 643-652 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  28. A neuro-emulator with embedded capabilities for generalized learning

    Aikens, VC., Delgado-Frias, JG., Pechanek, GG. & Vassiliadis, S., 1999, In : Journal of Systems Architecture. 45, p. 1219-1243 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  29. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  30. Agent based social simulation in markets

    Bertels, KLM. & Boman, M., 1999, WAEC'99: proceedings. Yiming Ye & Jiming Liu (eds.). S.l.: s.n., p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  31. Algorithm development for scalable processor systems based on transport triggered architectures

    Corporaal, H., 1999, Proceedings. AB Smolders & MP Haarlem, V. (eds.). Dwingeloo: ASTRON, p. 225-234 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  32. Capacitive threshold logic: a designer perspective

    Padure, MD., Dan, C., Cotofana, SD., Bodea, M. & Vassiliadis, S., 1999, CAS '99 proceedings. Vol. 1. S.l.: IEEE Society, p. 81-84 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  33. Computer architectuur, implementatie en realisatie

    Corporaal, H., 1999, ICT-zakboekje. TMA Bemelmans, PME Bra, D., M Looijen & G Oortmerssen, V. (eds.). Arnhem: Koninklijke PBNA, p. 569-663

    Research output: Chapter in Book/Report/Conference proceedingChapterProfessional

  34. Delft-Java dynamic translation

    Glossner, CJ. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 57-61 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  35. Efficient VLSI layouts of hypercubic networks

    Yeh, CH., Varvarigos, EA. & Parhami, B., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 98-105 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  36. Evaluation of a potential for automatic SIMD parallelization of embedded applications

    Manniesing, R., Karkowski, I. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 103-110 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  37. Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Eighth Asian Test Symposium: proceedings. Los Alamitos: IEEE, p. 185-191 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  38. Floating point to fixed point conversion of C code

    Cilio, AGM. & Corporaal, H., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 229-243 15 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  39. Global program optimization: register allocation of static scalar objects

    Cilio, AGM. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 52-57 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  40. Hardwired Paeth codec for portable network graphics (PNG)

    Hakkennes, EA. & Vassiliadis, S., 1999, Euromicro 99: proceedings. Vol. 2. S.l.: IEEE Society, p. 318-325 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  41. Hierarchical mixed simulation for intelligent interfaces of microsystems

    Niculiu, T., Cotofana, SD. & Manolescu, A., 1999, CAS '99 proceedings. Vol. 2. S.l.: IEEE Society, p. 515-518 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  42. Illegal state space identification for sequential circuit test generation

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Proceedings. D Borrione & R Ernst (eds.). Los Alamitos: IEEE, p. 741-746 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  43. Instruction set synthesis using operation pattern detection

    Arnold, M. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 413-420 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  44. ManArray processor interconnection network: an introduction

    Pechanek, GG., Vassiliadis, S. & Pitsianis, N., 1999, Euro-Par '99 Parallel Processing: proceedings (Lecture notes in computer science 1685). P Amestoy (ed.). Berlin: Springer, p. 761-765 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  45. March tests for word-oriented two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 1999, Eighth Asian Test Symposium: proceedings. Los Alamitos: IEEE, p. 53-60 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  46. Multimedia hardware accelerators

    Hakkennes, EA., 1999, S.l.: s.n.. 140 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  47. Multistatic FMCW radar for collision avoidance applications, optimization of the antenna configuration and improvement of the data processing

    Steenstra, HT., Muller, FL. & Swart, PJF., 1999, MIOP 99: conference proceedings.Vol. 2.. Portsmouth: Microwave Engineering Europe, p. 13-16 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  48. Network routing algorithms

    Varvarigos, EA. & Yeh, CH., 1999, Wiley encyclopedia of electrical and electronics engineering. New York: Wiley, p. 218-226

    Research output: Chapter in Book/Report/Conference proceedingChapterScientific

  49. Parallel algorithms on the rotation-exchange network - a trivalent variant of the star graph

    Yeh, CH. & Varvarigos, EA., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 303-309 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  50. Port interference faults in two-port memories

    Hamdioui, S. & van de Goor Ph D, AJ., 1999, Proceedings. S.l.: IEEE Society, p. 1001-1010 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  51. Qualitative company performance evaluation: linear discriminant analysis and neural network models

    Bertels, KLM., Jacques, JM., Neuberg, L. & Gatot, L., 1999, In : European Journal of Operational Research. 115, 3, p. 608-615 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  52. Remove: a computer architecture designed for modern VLSI technology

    Roos, S., Lamberts, R. & Corporaal, H., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 421-428 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  53. Serial binary multiplication with feed-forward neural networks

    Cotofana, SD. & Vassiliadis, S., 1999, In : Neurocomputing. 28, p. 1-19 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  54. Superscalar branch instruction processor

    Jeremiah, TL., Vassiliadis, S. & Blaner, B., 1999, CSCS-12: proceedings. Vol. 2. I Dumitrache & M Dobre (eds.). Bucharest: Editura Politehnica, p. 163-168 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  55. TTAs: missing the ILP complexity wall

    Corporaal, H., 1999, In : Journal of Systems Architecture. 45, p. 949-973 25 p.

    Research output: Contribution to journalArticleScientificpeer-review

  56. Testability of the Philips 80C51 micro-controller

    Konijnenburg, MH., van Linden, JT. & van de Goor Ph D, AJ., 1999, Proceedings. S.l.: IEEE Society, p. 820-829 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  57. The Paderborn University BSP (PUB) library design, implementation and performance

    Bonorden, O., Juurlink, BHH., von Otte, I. & Rieping, I., 1999, Proceedings of the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. B Werner (ed.). Los Alamitos: IEEE, p. 99-104 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  58. The \-scheduler: a multiwavelength scheduling switch

    Lang, JP., Varvarigos, EA. & Blumenthal, DJ., 1999, Proceedings. B Hajek & RS Sreenivas (eds.). Urbana: University of Illinois, p. 689-698 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  59. The effect of process switches on branch prediction accuracy

    Kisuki, T., Corporaal, H. & Knijnenburg, PMW., 1999, ASCI '99: proceedings. M Boasson, JA Kaandorp, JFM Tonino & MG Vosselman (eds.). Delft: Advanced School for Computing and Imaging, p. 81-88 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  60. The priority broadcast scheme for dynamic broadcast in hypercubes and related networks

    Yeh, CH., Varvarigos, EA. & Lee, H., 1999, Proceedings of the 7th symposium on the frontiers of massively parallel computation. Los Alamitos: IEEE, p. 294-301 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  61. The recursive grid layout scheme for VLSI layout of hierarchical networks

    Varvarigos, EA., Parhami, B. & Yeh, CH., 1999, IPPS/SPDP 1999 Proceedings. Los Alamitos: IEEE, p. 441-445 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  62. Towards the additional use of phase processing in multistatic FMCW radar, considerations and experimental results

    Swart, PJF., Steenstra, HT., Muller, FL., van der Zwan, WF., van Genderen, P., Ligthart, LP., Reijns, GL. & van Gemund, AJC., 1999, Conference proceedings. Vol. 1. London: Microwave Engineering Europe, p. 238-241 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  63. Transforming and parallelizing ANSI C programs using pattern recognition

    Boekhold, M., Karkowski, I. & Corporaal, H., 1999, High-performance computing and networking: proceedings (Lecture notes in computer science 1593). P Sloot, M Bubak, A Hoekstra & B Hertzberger (eds.). Berlin: Springer, p. 673-682 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  64. Vector ISA extension for sparse matrix-vector multiplication

    Vassiliadis, S., Cotofana, SD. & Stathis, P., 1999, Euro-Par '99 Parallel Processing: proceedings (Lecture notes in computer science 1685). P Amestoy (ed.). Berlin: Springer, p. 708-715 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  65. 1998
  66. Application of Transient Heat Flux Sensors to Resolve Time-Dependent Convective Heat Transfer from Wall-mounted Cubes

    Meinders, ER., Geuzebroek, MJ., Hanjalic, K. & Ortega, A., 1998, ASME Conference. Nelson, RA., Chopin, T. & Thynell, ST. (eds.). p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

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