1. 2011
  2. Improved Power Modeling of DDR SDRAMs

    Chandrasekar, K., Akesson, B. & Goossens, KGW., 2011, Proceedings 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 99-108 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Inverse Integer Transform in H.264/AVC Intra-frame Encoder

    Nadeem, M., Wong, JSSM. & Kuzmanov, GK., 2011, International Symposium on Electronic Design, Test and Applications (DELTA 2011). Bailey, D. & Demidenko, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 228-233 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. K-loops: Loop Transformations for Reconfigurable Architectures

    Dragomir, OS., 2011, 140 p.

    Research output: ThesisDissertation (TU Delft)

  5. Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

    Taouil, M. & Hamdioui, S., 2011, 16th IEEE European Test Symposium. Aas, EJ. & Anghel, L. (eds.). Piscataway, NJ, USA: IEEE Society, p. 45-50 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  6. Leakage-enhanced 3D-Stacked NEMFET-based Power Management Architecture for Autonomous Sensors Systems

    Enachescu, M., Voicu, GR. & Cotofana, SD., 2011, 15th International Conference on System Theory, Control and Computing (ICSTCC 2011). Enachescu, M. & Cascaval, P. (eds.). Piscataway, NJ, USA: IEEE Society, p. 218-223 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. Loop Distribution for K-Loops on Reconfigurable Architectures

    Dragomir, OS. & Bertels, KLM., 2011, Proceedings Design, Automation and Test in Europe Conference and Exhibition. Preas, K. (ed.). Leuven, Belgium: EDAA, p. 1548-1553 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2011.

    Research output: Contribution to conferencePosterProfessional

  9. Mesochronous NoC Technology for Power-Efficient GALS MPSoCs

    Ludovici, D., Strano, A., Gaydadjiev, GN. & Bertozzi, D., 2011, Fifth ACM Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC). Flich, J., Bertozzi, D., Skei, T. & Ludovici, D. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 27-30 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Modeling and Mitigating NBTI in Nanoscale Circuits

    Seyab, MSK. & Hamdioui, S., 2011, Proceedings of IEEE International On-Line Testing Symposium (IOLTS 2011). Nicolaidis, M., Paschalis, A., Gizopoulos, D. & Vera, X. (eds.). Piscataway, NJ, USA: IEEE Society, p. 3-8 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Multi-core Platforms for Beamforming and Wave Field Synthesis

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2011, In : IEEE Transactions on Multimedia. 13, 2, p. 235-245 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Multicore Architectures for Bioinformatics Applications

    Isaza Ramirez, S., 2011, Delft: S. Isaza Ramirez. 152 p.

    Research output: ThesisDissertation (TU Delft)

  13. NBTI Monitoring and Design for Reliability in Nanoscale Circuits

    Seyab, MSK., Haron, NZB., Hamdioui, S. & Catthoor, F., 2011, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011). Chapman, G., Salice, F., Joshi, PD. & Violante, M. (eds.). Piscataway, NJ, USA: IEEE Society, p. 68-76 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  14. NBTI-Aware Nanoscaled Circuit Delay Assessment and Mitigation

    Seyab, MSK. & Hamdioui, S., 2011, Proceedings of 3rd Workshop on Design for Reliability (DFR'11). Orailoglu, A., Michael, MK., Sazeides, Y. & Theocharides, T. (eds.). Crete, Greece: HiPEAC, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  15. Nexus: hardware support for task-based programming

    Meenderinck, CH. & Juurlink, BHH., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 442-445 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. On Correcting Cluster Errors in Nanoelectronic Memories

    Haron, NZB. & Hamdioui, S., 2011, Proceedings of 3rd Workshop on Design for Reliability (DFR'11). Orailoglu, A., Michael, MK., Sazeides, Y. & Theocharides, T. (eds.). Crete, Greece: HiPEAC, p. 63-68 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  17. On Defect Oriented Testing for Hybrid CMOS/memristor Memory

    Haron, NZB. & Hamdioui, S., 2011, 20th IEEE Asian Test Symposium 2011. Chatterjee, A., Patra, A., Kundu, S. & Ravi, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 353-358 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. On Modeling and Optimizing Cost in 3D Stacked-ICs

    Taouil, M., Hamdioui, S. & Marinissen, E., 2011, 6th IEEE International Design and Test Workshop during ICECS 2011. Sawan, M. & Harmanani, H. (eds.). Piscataway, NJ, USA: IEEE Society, p. 24-29 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  19. Optimizing Memory BIST Address Generator Implementations

    van de Goor, AJ., Kukner, H. & Hamdioui, S., 2011, Proceedings 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era. Bernard, S. & Efstathiou, C. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. PUMA: Placement Unification with Mapping and guaranteed throughput Allocation on an FPGA Using A Hardwired NoC

    Wahlah, MA. & Goossens, KGW., 2011, 14th Euromicro Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 88-98 11 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Parallel Access Schemes for Polymorphic Register Files: Motivation Study

    Ciobanu, CB., Kuzmanov, GK., Ramirez, A. & Gaydadjiev, GN., 2011, Proceedings 7th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems. de Bosschere et al, K. (ed.). Ghent, Belgium: HiPEAC, p. 127-130 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Parametrizing Multicore Architectures for Multiple Sequence Alignment

    Isaza Ramirez, S., Sanchez, F., Cabarcas, F., Ramirez, A. & Gaydadjiev, GN., 2011, ACM International Conference on Computing Frontiers 2011. Cascaval, C., Prasanna, V. & Trancoso, P. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  23. Power Minimisation for Real-time Dataflow Applications

    Nelson, AT., Moreira, O., Molnos, AM., Stuijk, S., Nguyen, BT. & Goossens, KGW., 2011, Proceedings of the International Conference on Digital System Design. Kitsos, P. (ed.). Piscataway: IEEE Society, p. 117-124 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  24. REFLECT: Rendering FPGAs to Multi-core Embedded Computing

    Cardoso, JMP., Bertels, KLM., Kuzmanov, GK., Nane, R. & Sima, VM., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hubner, M. (eds.). Berlin - Heidelberg: Springer, p. 261-291 291 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  25. Realistic Online Resource Management for Partially Reconfigurable Systems

    Lu, Y., 2011, 170 p.

    Research output: ThesisDissertation (TU Delft)

  26. Recursive Variable Expansion a transformation for Reconfigurable Computing

    Nawaz, Z., 2011, Delft: Zubair Nawaz. 150 p.

    Research output: ThesisDissertation (TU Delft)

  27. Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories

    Haron, NZB. & Hamdioui, S., 2011, In : ACM Journal on Emerging Technologies in Computing Systems. 7, 1, p. 1-19 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. ReverseAge: an Online NBTI Combating Technique Using Time Borrowing

    Seyab, MSK. & Hamdioui, S., 2011, 6th IEEE International Design and Test Workshop (IDT 2011). Sawan, M. & Harmanani, H. (eds.). Piscataway, NJ, USA: IEEE Society, p. 36-41 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  29. Runtime Extraction of Memory Access Information from the Application Source Code

    Ostadzadeh, SA., Corina, M., Galuzzi, C. & Bertels, KLM., 2011, Proceedings of the 2011 International Conference on High Performance Computing & Simulation (HCPS 2011). Smari, WW. & Gentzsch et al., W. (eds.). Piscataway: IEEE Society, p. 647-655 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  30. Runtime Support for Heterogeneous Multi-core Systems

    Sabeghi, M., 2011, Delft: M. Sabeghi. 176 p.

    Research output: ThesisDissertation (TU Delft)

  31. Scalability Evaluation of a Polymorphic Register File: a CG Case Study

    Ciobanu, CB., Martorell, X., Kuzmanov, GK., Ramirez, A. & Gaydadjiev, GN., 2011, 2011 Conference on Architecture of Computing Systems. Berekovic, M., Fornaciari, W., Brinkschulte, U. & Silvano, C. (eds.). Heidelberg, Germany: Springer, p. 13-25 13 p. (Lecture Notes in Computer Science; vol. 6566).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  32. Scaling HMMER Performance on Multicore Architectures

    Isaza Ramirez, S., Houtgast, E., Sanchez, F., Ramirez, A. & Gaydadjiev, GN., 2011, IEEE International Workshop on Multicore Computing Systems, MuCoCoS 2011. Barolli, Xhafa, F. & Pllana, S. (eds.). Piscataway, NJ, USA: IEEE, p. 618-623 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  33. Sequence alignment application model for multi- and manycore architectures

    Isaza, S., Houtgast, E. & Gaydadjiev, GN., 2011, In : International Journal on Information Technologies and Security. September 2011, p. 3-20 18 p.

    Research output: Contribution to journalArticleScientificpeer-review

  34. Stacking Order Impact on Overall 3D Die-to-Wafer Stacked-IC Cost

    Taouil, M. & Hamdioui, S., 2011, IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Kraemer, R., Steininger, A., Pawlak, A. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 335-340 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  35. Survey of Fault Tolerance Techniques for Shared Memory Multicore/Multiprocessor Systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2011, 6th IEEE International Design and Test Workshop (IDT) during ICECS 2011. Sawan, M. & Harmanani, H. (eds.). Piscataway, NJ, USA: IEEE Society, p. 12-17 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  36. System-Level Design Space Exploration of Reconfigurable Architectures

    Sigdel, K., 2011, 170 p.

    Research output: ThesisDissertation (TU Delft)

  37. Targeting Code Diversity with Run-time Adjustable Issue-slots in a Chip Multiprocessor

    Anjam, F., Nadeem, M. & Wong, JSSM., 2011, Proceedings Design, Automation and Test in Europe Conference and Exhibition. Preas, K. (ed.). Leuven, Belgium: EDAA, p. 1358-1363 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  38. Task Scheduling Strategies for Dynamic Reconfigurable Processors in Distributed Systems

    Nadeem, MF., Ostadzadeh, SA., Wong, JSSM. & Bertels, KLM., 2011, Proceedings of the 2011 International Conference on High Performance Computing & Simulation. Smari, WW. & Gentzsch et al., W. (eds.). Piscataway, NJ, USA: IEEE Society, p. 90-97 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  39. Technology Aware Network-on-Chip Connectivity and Synchronization Design

    Ludovici, D., 2011, 150 p.

    Research output: ThesisDissertation (TU Delft)

  40. Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost

    Taouil, M., Hamdioui, S., Beenakker, CIM. & Marinissen, E., 2011, In : Journal of Electronic Testing: theory and applications. 10836, p. 1-11 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  41. Testing for Parasitic Memory Effect in SRAMs

    Irobi, IS., Al-Ars, Z., Hamdioui, S. & Thibeault, C., 2011, 20th IEEE Asian Test Symposium 2011. Chatterjee, A., Patra, A., Kundu, S. & Ravi, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  42. The Small Signal Amplification of the Gated Diode Operated in Breakdown Regime

    Rusu, A., Dobrescu, D., Enachescu, M., Burileanu, C. & Rusu, A., 2011, Proceedings of 34th International Semiconductor Conference (CAS 2011). Dascalu, D. & Rusu, A. (eds.). Piscataway, NJ, USA: IEEE Society, p. 321-324 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  43. Towards "Zero-energy" using NEMFET-based Power Management for 3D Hybrid Stacked ICs

    Voicu, GR., Enachescu, M. & Cotofana, SD., 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011). Moritz, CA. & O`Connor, I. (eds.). Piscataway, NJ, USA: IEEE Society, p. 203-209 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  44. Universal Processor Architecture for Biomedical Implants: The SiMS Project

    Strydis, C., 2011, 315 p.

    Research output: ThesisDissertation (TU Delft)

  45. Vector Processor Customization for FFT

    Spinean, B., Kuzmanov, GK. & Gaydadjiev, GN., 2011, International Conference on Embedded Computer Systems: Architecture Modeling and Simulation. Carro, L. & Pimentel, A. (eds.). Piscataway: IEEE Society, p. 110-117 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  46. Yield improvement and test cost optimization for 3D stacked ICs

    Hamdioui, S. & Taouil, M., 2011, 20th IEEE Asian Test Symposium 2011. Chatterjee, A., Patra, A., Kundu, S. & Ravi, S. (eds.). Piscataway, NJ, USA: IEEE Society, p. 480-485 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  47. hArtes: Holistic Approach to Reconfigurable Real-Time Embedded Systems

    Kuzmanov, GK., Sima, VM., Bertels, KLM., Coutinho, G., Luk, W., Marchiori, G., Tripiccione, R. & Ferrandi, F., 2011, Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Cardoso, JMP. & Hübner, M. (eds.). Berlin - Heidelberg: Springer, p. 91-116 290 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeChapterScientific

  48. 2010
  49. 3D compaction: a novel blocking-aware algorithm for online hardware task scheduling and placement on 2D partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2010, 6th Intl. symp. ARC 2010. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 194-206 13 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  50. A 3D-audio reconfigurable processor

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 107-110 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  51. A Novel Virtual Age Reliability Model for Time-toFailure Prediction

    Wang, Y. & Cotofana, SD., 2010, IEEE International Integrated Reliability Workshop Final Report. Young, C. & Geilenkeuser, R. (eds.). Piscataway, NJ, USA: IEEE Society, p. 102-105 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  52. A TDM slot allocation flow based on multipath routing in NoCs

    Stefan, RA. & Goossens, KGW., 2010, In : Microprocessors and Microsystems. p. 1-9 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  53. A VLIW softcore processor with dynamically adjustable issue-slots

    Anjam, F., Nadeem, M. & Wong, JSSM., 2010, 2010 intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  54. A case for hardware task management support for the StarSS programming

    Meenderinck, CH. & Juurlink, BHH., 2010, 13th Euromicro conf. on digital systems design, architectures, methods and tools. s.n. (ed.). Piscataway: IEEE Society, p. 347-354 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  55. A communication aware online task scheduling algorithm for FPGA-based partially reconfigurable systems

    Lu, Y., Thomas, TM., Bertels, K. & Gaydadjiev, GN., 2010, 18th IEEE Field-programmable custom computing machines. Sass, R. & Tessier, R. (eds.). Los Alamitos, CA: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  56. A composable, energy-managed, realtimeMPSOC platform

    Goossens, KGW., Molnos, AM., Ambrose, JA., Nelson, AT., Stefan, RA. & Cotofana, SD., 2010, 12th Intl. optimization electrical and electronic equipment. s.n. (ed.). s.l.: IEEE Society, p. 870-876 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  57. A library of dual-clock FIFOs for cost-effective and flexible MPSoCs design

    Strano, A., Ludovici, D. & Bertozzi, D., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 20-27 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  58. A minimalistic for reconfigurable WFS-based immersive-audio

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2010, 2010 Intl. conf. on reconfigurable computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  59. A modified merging approach for datapath configuration time reduction

    Fazlali, M., 2010, Reconfigurable computing: architectures, tools and applications. Sirisuk, P., Morgan, F., El-Ghazawi, T. & Amano, H. (eds.). Berlijn: Springer, p. 318-328 11 p. (Lecture Notes in Computer Science; vol. 5992).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  60. A multidimensional software cache for scratchpad-based systems

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2010, In : International Journal of Embedded and Real-Time Communication Systems. 1, 4, p. 1-20 20 p.

    Research output: Contribution to journalArticleScientificpeer-review

  61. A multiported register file with register renaming for configurable softcore VLIW processors

    Anjam, F., Wong, JSSM. & Nadeem, MF., 2010, 2010 Intl. conf. on field programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  62. A novel HDL coding style to reduce power consumption for reconfigurable devices

    Thomas, TM., Theodoropoulos, D., Bertels, KLM. & Gaydadjiev, GN., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 295-299 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  63. A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices

    Thomas, TM., Hur, JY., Bertels, K. & Gaydadjiev, GN., 2010, 2010 IEEE 8th symp. on application specific processors. s.n. (ed.). CA, USA: IEEE Society, p. 105-110 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  64. A parallel FPGA design of the Smith-waterman traceback

    Nawaz, Z., Nadeem, M., van Someren, J. & Bertels, KLM., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 454-459 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  65. A polymorphic register file for matrix operations

    Ciobanu, CB., Kuzmanov, GK., Gaydadjiev, GN. & Ramirez, A., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 241-249 9 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  66. A shared reconfigurable VLIW multiprocessor system

    Anjam, F., Wong, S. & Nadeem, MF., 2010, IPDPS 2010 conf. 24th IEEE intl. parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  67. A unified addition structure for moduli set 2n-1, 2n, 2n+1 based on a novel RNS representation

    Timarchi, S., Fazlali, M. & Cotofana, SD., 2010, ICCD 2010. s.n. (ed.). Piscataway: IEEE Society, p. 247-252 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  68. Advanced NEMS-based power management for 3D stacked integrated circuits

    Enachescu, M., Voicu, GR. & Cotofana, SD., 2010, 2010 Intl. conf. on energy aware computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  69. An attitude determination system suitable for a spacecraft

    Amini, R., Gill, EKA. & Gaydadjiev, GN., 2010, IPC No. aanvrager: TU Delft, Patent No. NL48.293-VB, Priority date 1 Jan 1800

    Research output: Patent

  70. An efficient FPGA design of reverse converter for the moduli set {2n+2, 2n+1, 2n}

    Gbolagade, KA., Voicu, GR. & Cotofana, SD., 2010, Advanced computer architecture and compilation for high-performance and embedded systems. s.n. (ed.). s.l.: s.n., p. 117-120 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  71. An efficient realization of forward integer transform in H.264/AVC intra-frame encoder

    Nadeem, M., Wong, S. & Kuzmanov, GK., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 71-78 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  72. An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set

    Gbolagade, KA., Chaves Fernandes, R., Sousa, L. & Cotofana, SD., 2010, IEEE intl. symposium on circuits and systems. Piscataway: IEEE Society, p. 2103-2106 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  73. Badwidth analysis of functional interconnects used as test access mechanism

    van den Berg, A., Ren, P., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2010, In : Journal of Electronic Testing: theory and applications. 26, 4, p. 453-464 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  74. Bit line coupling memory tests for single cell fails in SRAMs

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2010, 28th IEEE VLSI test symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  75. Buffered crossbar fabrics based on network on chip

    Mhamdi, LL., Goossens, KGW. & Varela Senin, I., 2010, 8th annual communication networks and services research conference. s.n. (ed.). Piscataway: IEEE Society, p. 74-79 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  76. Collaboration of reconfigurable processors in grid computing for multimedia kernels

    Ahmadi, M., Shahbahrami, A. & Wong, JSSM., 2010, Grid and Pervasive Computing 2010. s.n. (ed.). Berlijn: Springer, p. 5-14 10 p. (Lecture Notes in Computer Science; vol. 6104/2010).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  77. Composable dynamic voltage and frequency scaling and power management for dataflow applications

    Goossens, KGW., She, D., Milutinovic, A. & Molnos, AM., 2010, 13th euromicro conf. on digital system design. s.n. (ed.). Piscataway: IEEE Society, p. 107-114 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  78. Composable processor virtualization for embedded systems

    Molnos, AM., Milutinovic, A., She, D. & Goossens, KGW., 2010, 1st workshop on Computer Architecture and operating system co-design. s.n. (ed.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  79. Conservative application-level performance analysis through simulation of MPSoCs

    Nelson, AT., Hansson, A., Corporaal, H. & Goossens, KGW., 2010, 7th workshop on embedded systems for real-time multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  80. Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

    Ludovici, D., Gilabert, F., Gaydadjiev, GN. & Bertozzi, D., 2010, 3rd Intl. workshop on network on chip architectures. s.n. (ed.). Piscataway: IEEE Society, p. 37-42 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  81. Data structure, method and system for address lookup

    Sourdis, I., Smet de, R., Stefanakis, G. & Gaydadjiev, GN., 2010, Patent No. NL 2002799, Priority date 26 Oct 2010

    Research output: Patent

  82. Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

    Ludovici, D., Strano, A., Gaydadjiev, GN., Benini, L. & Bertozzi, D., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 679-684 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  83. Detecting memory faults in the presence of bit line coupling in SRAM devices

    Irobi, IS., Al-Ars, Z. & Hamdioui, S., 2010, Intl. test conference 2010. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  84. Digital analysis of papers for the authentication and dating of art

    Pourebrahimi, B., Van Der Lubbe, J. C. A. & Dietz, G., 2010, Proceedings of the 12th IASTED International Conference on Signal and Image Processing, SIP 2010. p. 93-100 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  85. Dynamic profiling framework in the Delft workbench

    Ostadzadeh, SA. & Bertels, KLM., 2010.

    Research output: Contribution to conferencePosterScientific

  86. Dynamically reconfigurable register file for a softcore VLIW processor

    Wong, JSSM., Anjam, F. & Nadeem, MF., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  87. ECC design for fault-tolerant crossbar memories: a case study

    Haron, NZB., Hamdioui, S. & Ahyadi, Z., 2010, 5th Intl. design and test workshop. Elahi, I., Ivanov, A., Zorian, Y. & Salem, A. (eds.). Piscataway: IEEE Society, p. 61-666 606 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  88. Effect of the degree of neighborhood on resource discovery in ad hoc grids

    Abdullah, MT., Bertels, K., Alima, LO. & Nawaz, Z., 2010, 23rd Intl. conf. ARCS 2010. Muller-Schloer, C., Karl, W. & Yehia, S. (eds.). Heidelberg: Springer, p. 174-186 13 p. (Lecture Notes in Computer Science; vol. 5974).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  89. Effective reverse conversion in residue number system processors

    Gbolagade, KA., 2010, Delft. 160 p.

    Research output: ThesisDissertation (TU Delft)

  90. Efficient datapath merging for the overhead reduction of run-time reconfigurable systems

    Fazlali, M., Zakerolhosseini, A. & Gaydadjiev, GN., 2010, In : Journal of Supercomputing: an international journal of high-performance computer design, analysis and use. 52, 3

    Research output: Contribution to journalArticleScientificpeer-review

  91. Efficient hardware task reuse and interrupt handling for FPGA-based partially reconfigurable systems

    Lu, Y., Gaydadjiev, GN. & Bertels, KLM., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 324-327 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  92. Efficient task scheduling for runtime reconfigurable systems

    Fazlali, M., Sabeghi, M., Zakerolhosseini, A. & Bertels, KLM., 2010, In : Journal of Systems Architecture. 56, 11, p. 623-632 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  93. Evaluation of parallel H.264 decoding strategies for the cell broadband engine

    Chi, C., Juurlink, B. & Meenderinck, CH., 2010, 2010 Intl. conference on supercomputing. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 105-114 10 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  94. Evaluation of runtime task mapping heuristics with rSesame - a case study

    Sigdel, K., Thompson, M., Galuzzi, C., Pimentel, A. & Bertels, K., 2010, Design, automation & test in Europe. s.n. (ed.). s.l.: s.n., p. 831-836 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  95. Extending the cell SPE with energy efficient branch prediction

    Briejer, M., Meenderinck, CH. & Juurlink, BHH., 2010, 16th intl. Euro-Par conf.. D'Ambra, P., Guarracino, M. & Talia, D. (eds.). Berlijn: Springer, p. 304-315 12 p. (Lecture Notes in Computer Science; vol. 6271).

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  96. Fast smith-waterman hardware implementation

    Nawaz, Z., Bertels, KLM. & Sümbül, HE., 2010, IPDPS 2010 Conference 24th Intl. Parallel and Distributed processing symposium. s.n. (ed.). Piacataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  97. Fine-grain fault diagnosis for FPGA logic blocks

    Tzilis, S., Sourdis, I. & Gaydadjiev, GN., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 154-161 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  98. General purpose computing with reconfigurable acceleration

    Brandon, AAC., Sourdis, I. & Gaydadjiev, GN., 2010, 2010 intl. conf on field programmable logic and applications. s.n. (ed.). Piscataway: IEEE Society, p. 588-591 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  99. Growing on the inside: soulful characters for video games

    Bidarra, AR., Schaap, R. & Goossens, KGW., 2010, Proceedings of IEEE Conference on Computational Intelligence and Games. s.n. (ed.). Los Alamitos, CA, USA: IEEE Society, p. 337-344 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  100. HArtes: hardware-software codesign for heterogeneous multicore platforms

    Bertels, KLM., Sima, VM., Yankova, YD. & Kuzmanov, GK., 2010, In : IEEE Micro. 30, 5, p. 88-97 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  101. Hand segmentation by fusing 2D and 3D data

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2010, Intl conf. on Computer modeling and simulation. s.n. (ed.). Los Alamitos, CA: IEEE Society, p. 99-103 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  102. High performance and resource efficient biological sequence alignment

    Hasan, L., Al-Ars, Z. & Taouil, M., 2010, IEEE EMB. s.n. (ed.). s.n., p. 1767-1770 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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