501 - 600 out of 1,563Page size: 100
  1. Conference contribution › Scientific › Peer-reviewed
  2. A padding processor for MPEG-4

    Kuzmanov, G., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 470-474 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. A parallel FPGA design of the Smith-waterman traceback

    Nawaz, Z., Nadeem, M., van Someren, J. & Bertels, KLM., 2010, Proc. 2010 Intl. conf. on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 454-459 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. A partially buffered crossbar packet switching architecture and its scheduling

    Mhamdi, LL., 2008, IEEE Intl. Symposium on Computers and Communications. s.n. (ed.). s.l.: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. A peer-to-peer agent auction

    Ogston, EFYL. & Vassiliadis, S., 2002, Proceedings of the first international joint conference on Autonomous agents and multiagent systems Part I. Castelfranchi, C. & Johnson, WL. (eds.). New York: Association for Computing Machinery (ACM), p. 151-159 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. A performance model for network processor architectures in packet processing system

    Ahmadi, M. & Wong, S., 2007, 19th IASTED Parallel and distributed computing and systems. Zheng SQ (ed.). Anaheim: ACTA Press, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. A platform for RFID security and privacy administration

    Rieback, M., Gaydadjiev, GN., Crispo, B., Hofman, R. F. H. & Tanenbaum, AS., 2006, Proc. 20th Large Installation System Administration Conf.. s.n. (ed.). Berkeley, USA: USENIX, p. 89-102 14 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. A polymorphic register file for matrix operations

    Ciobanu, CB., Kuzmanov, GK., Gaydadjiev, GN. & Ramirez, A., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 241-249 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. A power aware HW/SW partitioning for a DVB-H receiver module

    Koryfides, I., Cotofana, SD. & van Gassel, J., 2006, 17th Annual Workshop on Circuits Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 293-299 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. A pragmatic gaze on stochastic resonance based variability tolerant memristance enhancement

    Ntinas, V., Rubio, A., Sirakoulis, G. C. & Cotofana, S. D., 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2019-May. 5 p. 8702792

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. A predictor-based power-saving policy for DRAM memories

    Thomas, G., Chandrasekar, K., Akesson, B., Juurlink, BHH. & Goossens, KGW., 2012, 15th Euromicro conference on digital system design. s.n. (ed.). s.n.: Euromicro, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  12. A profiling framework for design space exploration in heterogeneous systems context

    Sigdel, K., Meeuws, RJ. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 363-368 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. A programmable ANSI C transformation engine

    Boekhold, M., Karkowski, I., Corporaal, H. & Cilio, AGM., 1999, Compiler construction: proceedings (Lecture notes in computer science 1575). S Jähnichen (ed.). Berlin: Springer, p. 292-295 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  14. A quantative prediction model for hardware/software partitioning

    Meeuws, RJ., Yankova, YD., Bertels, K., Gaydadjiev, GN. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 735-739 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  15. A reconfigurable beamformer for audio applications

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 2009 IEEE 7th symposium on application specific processors. s.n. (ed.). Piscataway: IEEE Society, p. 80-87 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  16. A reconfigurable hardware based embedded scheduler for buffered crossbar switches

    Mhamdi, L., Kachris, C. & Vassiliadis, S., 2006, Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 143-149 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. A reconfigurable perfect-hashing scheme for packet inspection

    Sourdis, I., Pnevmatikatos, DN., Wong, JSSM. & Vassiliadis, S., 2005, Proceedings of 15th International Conference on Field Programmable Logic and Applications (FPL 2005). Rissa, T., Wilton, S. & Leong, P. (eds.). IEEE Society, p. 644-647 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  18. A reconfigurable platform for multi-service edge routers

    Kachris, C. & Vassiliadis, S., 2007, 20th Symposium on integrated circuits and systems design. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 165-169 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  19. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  20. A reverse converter for the new 4-moduli set {2n+3, 2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international conference on electronics circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 113-116 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  21. A run-time modulo scheduling by using a binary translation mechanism

    Ferreira, R., Denver, W., Pereira, M., Quadros, J., Carro, L. & Wong, S., 2014, Proceedings - 2014 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Galuzzi, C. & Veidenbaum, AV. (eds.). Piscataway, NJ, USA: IEEE Society, p. 75-82 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  22. A run-time task migration scheme for an adjustable issue-slots multi-core processor

    Anjam, F., Kong, Q., Seedorf, RAE. & Wong, JSSM., 2012, 8th International symposium on applied reconfigurable computing. s.n. (ed.). s.l.: s.n., p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  23. A scalable, multi-thread, multi-issue array processor architecture for DSP applications based on extended tomasulo scheme

    Berekovic, M. & Niggemeier, T., 2006, Embedded Computer Systems: Architectures, Modeling, and Simulation. Vassiliadis, S., Wong, S. & Hamalainen, TD. (eds.). Heidelberg: Springer, p. 289-298 10 p. (Lecture Notes in Computer Science; vol. 4017).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  24. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  25. A shared polyhedral cache for 3D wide-I/O multi-core computing platforms

    Lefter, M., Voicu, GR. & Cotofana, SD., 2015, Proceedings - 2015 IEEE International Symposium on Circuits and Systems. de Medeiras Silva, M. (ed.). Piscataway, NJ, USA: IEEE Society, p. 425-428 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  26. A shared reconfigurable VLIW multiprocessor system

    Anjam, F., Wong, S. & Nadeem, MF., 2010, IPDPS 2010 conf. 24th IEEE intl. parallel and distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  27. A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications

    Beyranvand Nejad, A., Molnos, AM. & Goossens, KGW., 2013, 19th IEEE International conference on embedded and real-time computing systems and applications. s.n. (ed.). Piscataway: IEEE Society, p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  28. A sparse VLIW instruction encoding scheme compatible with generic binaries

    Brandon, A., Hoozemans, J., Van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck, A. C. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers (IEEE), 7 p. 7393361

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  29. A static low-power, high-peformance 32-bit carry skip adder

    Chirca, K., Schulte, M., Glossner, CJ., Wang, H., Mamidi, S., Balzola, P. & Vassiliadis, S., 2004, Architectures, methods and tools. Selvaraj, H. (ed.). Piscataway: IEEE, p. 615-619 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  30. A sum of absolute differences implementation in FPGA hardware

    Wong, JSSM., Vassiliadis, S. & Cotofana, SD., 2002, EUROMICRO 2002; Proceedings of the 28th EUROMICRO Conference. Fernandez, M. (ed.). Piscataway, NJ. USA: IEEE Society, p. 183-188 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  31. A survey of autonomic computing systems

    Nami, MR. & Bertels, K., 2007, The third international conference on autonomic and autonomous systems. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  32. A survey of peer-to-peer networks

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2005, Proceedings of the SAFE & ProRISC 2005. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 570-577 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  33. A survey on low-power techniques for single and multicore systems

    Zandrahimi, M. & Al-Ars, Z., 2014, Proceedings 3rd International Conference on Context-Aware Systems and Applications. Mansoor, W., Maamar, Z. & Rabhi, F. (eds.). Ghent, Belgium: EAI, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  34. A systolic architecture for the Smith-Waterman algorithm with high performance cell design

    Hasan, L., Khawaya, YM. & Bais, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 35-42 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  35. A turnstile based single electron memory element

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, SAFE 2001: proceedings. Utrecht: STW Technology Foundation, p. 103-108 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  36. A two-phase practical parallel algorithm for construction of huffman codes

    Ostadzadeh, SA., Maryam Elahi, B., Tabrizi, ZZ., Amir Moulavi, M. & Bertels, K., 2007, 2007 intl. conf. on Parallel and distributed processing techniques and applicationss. Arabnia HR (ed.). USA: CSREA Press, p. 284-291 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  37. A unified addition structure for moduli set 2n-1, 2n, 2n+1 based on a novel RNS representation

    Timarchi, S., Fazlali, M. & Cotofana, SD., 2010, ICCD 2010. s.n. (ed.). Piscataway: IEEE Society, p. 247-252 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  38. A user-level library for fault tolerance on shared memory multicore systems

    Mushtaq, H., Al-Ars, Z. & Bertels, KLM., 2012, 15th IEEE symposium on design and diagnostics of electronic circuits and systems. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  39. A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

    Celinski, P., Cotofana, SD. & Abbott, D., 2003, Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003. Mira, J. & Álvarez, JR. (eds.). Berlin: Springer, p. 73-80 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  40. Accelarating color space conversion using extended subwords and the matrix register file

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2006, Eighth IEEE international Symposium on multimedia. Piscataway: IEEE Society, p. 37-44 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  41. Accelerating complex brain-model simulations on GPU platforms

    Nguyen, HAD., Al-Ars, Z., Smaragdos, G. & Strydis, C., 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ, USA: IEEE Society, p. 974-979 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  42. Accelerating the secure remote password protocol using reconfigurable hardware

    Groen, PT., Hämäläinen, P., Juurlink, BHH. & Hämäläinen, T., 2004, 2004 Computing Frontier Conference. New York: Association for Computing Machinery (ACM), p. 471-480 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  43. Acceleration of Smith-Waterman using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  44. Acceleration of biological sequence alignment using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 233-237 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  45. Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

    Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  46. Achieving fanout capabilities in single electron encoded logic networks

    Lageweg, C., Cotofana, SD. & Vassiliadis, S., 2001, Proceedings. Vol. 2. Piscataway: IEEE Society, p. 1383-1386 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  47. Adapting communication for adaptable processors: a multi-axis reconfiguration approach

    Santos, PC., Nazar, GL., Anjam, F. & Wong, JSSM., 2012, International conference on ReConFigurable computing and FPGAs. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  48. Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs

    Monteiro OliveiraCortez, AM., van der Leest, V., Maes, R., Schrijen, GJ. & Hamdioui, S., 2013, IEEE International symposium on hardware-oriented security and trust. s.n. (ed.). Piscataway: IEEE Society, p. 35-40 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  49. Adaption to dynamic resource availability in ad hoc grids through a learning mechanism

    Pourebrahimi, B. & Bertels, KLM., 2008, 2008 IEEE 11th Intl. Conf. on Computational Science and Engineering. s.n. (ed.). s.l.: s.n., p. 171-178 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  50. Adaptive ILP Control to increase Fault Tolerance for VLIW Processors

    Sartor, A. L., Wong, S. & Beck, A. C. S., Jul 2016, Application-specific Systems, Architectures and Processors (ASAP), 2016 IEEE 27th International Conference on. London, UK: IEEE, p. 9-16 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  51. Adaptive agent-based resource management for GRID

    Abdullah, MT., Bertels, KLM. & Vassiliadis, S., 2006, 12th Annual conference of the advanced school for computing and imaging. Lelieveldt, B. P. F., Haverkort, B., de Laat, C. T. A. M. & Heijnsdijk, J. W. J. (eds.). Delft: ASCI, p. 420-428 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  52. Adaptive clock scheduling for pipelined structures

    Kuiper, B. & Cotofana, SD., 2009, 2009 IEEE/ACM international symposium on nanoscale architectures. s.n. (ed.). Piscataway: IEEE Society, p. 65-68 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  53. Adaptive gaussian mixture for skin color segmentation

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2008, Proceeding of World Academy of Science, Engineering and Technology. s.n. (ed.). s.l.: WASET org., p. 1-6 6 p. (World Academy of Science, Engineering and Technology. Proceedings; vol. 31).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  54. Address and data scrambling: causes and impact on memory tests

    van de Goor, AJ. & Schanstra, I., 2002, International workshop on Electronic design, test, and applications. Renovell, M. & et al. (eds.). Piscataway, NJ, USA: IEEE Society, p. 128-137 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  55. Advanced NEMS-based power management for 3D stacked integrated circuits

    Enachescu, M., Voicu, GR. & Cotofana, SD., 2010, 2010 Intl. conf. on energy aware computing. s.n. (ed.). Piscataway: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  56. Advanced Profiling of Applications for Heterogeneous Multi-Core Platforms

    Bertels, KLM., Meeuws, RJ. & Ostadzadeh, SA., 2011, Proceedings of 2011 International Conference on Engineering of Reconfigurable Systems & Algorithms. Plaks, TP. (ed.). CSREA Press, p. 171-183 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  57. Aelite: a flit-synchronous network on chip with composable and predictable services

    Hansson, A., Subburaman, M. & Goossens, KGW., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 250-255 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  58. Agent based local ad hoc grids

    Abdullah, MT. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 284-287 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  59. Agent toolkits for ad hoc grids

    Abdullah, MT. & Bertels, K., 2009, Proceedings of the 1st international workshop on distributed computing in ambient environments. Brimkmann, A., Eikerling, H-J. & Zaheer Aziz, M. (eds.). s.l.: s.n., p. 49-58 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  60. Aging mitigation in memory arrays using self-controlled bit-flipping technique

    Gebregiorgis, A., Ebrahimi, M., Kiamehr, S., Oboril, F., Hamdioui, S. & Tahoori, MB., 2015, Proceedings - 20th Asia and South Pacific Design Automation Conference. Uchiyama, K. (ed.). Piscataway, NJ, USA: IEEE Society, p. 231-236 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  61. Algorithmic Skeletons for Stream Programming in Embedded Heterogeneous Parallel Image Processing

    Caarls, W., Jonker, PP. & Corporaal, H., 2006, Proc. 20th IEEE International Parallel & Distributed Processing Symposium. s.n. (ed.). Rhodos: s.l., p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  62. Algorithms for the automatic extension of an instruction-set

    Galuzzi, C., Theodoropoulos, D., Meeuws, RJ. & Bertels, K., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 548-553 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  63. Alternatives in FPGA-based SAD implementations

    Wong, JSSM., Stougie, B. & Cotofana, SD., 2002, 2002 IEEE international conference on field-programmable technology (FPT). Piscataway: IEEE Society, p. 449-452 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  64. An 8-point IDCT computing resource implemented on a trimedia/CPU64 reconfigurable functional unit

    Sima, M., Cotofana, SD., van Eijndhoven, JTJ. & Vassiliadis, S., 2001, Proceedings. F Karelse (ed.). Utrecht: STW Technology Foundation, p. 211-218 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  65. An Accelerator for Posit Arithmetic Targeting Posit Level 1 BLAS Routines and Pair-HMM

    van Dam, L., Peltenburg, J., Al-Ars, Z. & Hofstee, H. P., 2019, CoNGA'19 Proceedings of the Conference for Next Generation Arithmetic 2019. New York, NY: Association for Computing Machinery (ACM), p. 5:1--5:10 10 p. 5

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  66. An Efficient GPU-based de Bruijn Graph Construction Algorithm for Micro-Assembly

    Ren, S., Ahmed, N., Bertels, K. & Al-Ars, Z., 2018, Proceedings - 2018 IEEE 18th annual IEEE International Conference on BioInformatics and BioEngineering (BIBE 2018). Bourbakis, N. G. & Kavraki, D. (eds.). Piscataway, NJ, USA: IEEE, p. 67-72 6 p. 8567459

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  67. An Efficient Hardware Design for Intra-prediction in H.264/AVC Decoder

    Nadeem, M., Wong, JSSM. & Kuzmanov, GK., 2011, Saudi International Electronics, Communications and Photonics Conference 2011 (SIECPC). s.n. (ed.). Piscataway, NJ, USA: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  68. An FPGA Bridge Preserving Traffic Quality of Service for On-Chip Network-Based Systems

    Beyranvand Nejad, A., Escudero Martinez, M. & Goossens, KGW., 2011, Design, Automation and Test in Europe Conference and Exhibition (DATE 2011). Al-Hashimi, BM. (ed.). Leuven, Belgium: EDAA, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  69. An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

    Houtgast, E., Sima, VM., Bertels, K. & Al-Ars, Z., 28 Dec 2015, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV. Soudris, D. & Carro, L. (eds.). Piscataway, NJ, USA: IEEE Society, p. 221-227 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  70. An Image Processing VLIW Architecture for Real-Time Depth Detection

    Iorga, D., Nane, R., Lu, Y., van Dalen, E. & Bertels, K., 2016, Proceedings - 28th IEEE International Symposium on Computer Architecture and High Performance Computing: SBAC-PAD 2016. Baldassin, A. (ed.). Piscataway: IEEE, p. 158-165 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  71. An Industrial Case Study of Low Cost Adaptive Voltage Scaling Using Delay Test Patterns

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2018, Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, p. 999-1000 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  72. An Instruction to Accelerate Software Caches

    Pereira de Azevedo Filho, AP. & Juurlink, BHH., 2011, Proceedings of the 2011 Conference on Architecture of Computing Systems. Berekovic, M., Fornaciari, W., Brinkschulte, U. & Silvano, C. (eds.). Heidelberg: Springer, p. 158-170 13 p. (Lecture Notes in Computer Science; vol. LNCS 6566).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  73. An OCM based shared memory controller for virtex 4

    Breijer, B., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 692-696 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  74. An analysis of rule-set databases in packet classification

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 110-115 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  75. An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability

    Yang, B., Grandhi, S., Spagnol, C., Popovici, E. & Cotofana, S., 2016, Proceedings - 27th Irish Signals and Systems Conference. Curran, K. (ed.). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  76. An approach for optimal bandwidth allocation in packet processing systems

    Ahmadi, M. & Wong, S., 2008, CNSR 2008 conference. s.n. (ed.). s.l.: s.n., p. 208-214 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  77. An efective routing algorithm to avoid unnecessary link abandon in 2D mesh NoCs

    Chen, C. & Cotofana, SD., 2013, 16th Euromicro Conference on Digital System Design. s.n. (ed.). Piscataway: IEEE Society, p. 311-318 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  78. An effective new CRT based reverse converter for a novel moduli set { 2^(2n+1)-1, 2^(2n+1), 2^(2n)-1 }

    Bankas, EK., Gbolagade, KA. & Cotofana, SD., 2013, Proceedings 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors. El-Ghawazi, T. & Smith et al, M. (eds.). Los Alamitos, CA , USA: IEEE, p. 142-146 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  79. An efficient RNS to binary converter using the moduli set {2n+1, 2n, 2n-1}

    Gbolagade, KA. & Cotofana, SD., 2008, Conference on Design of Circuits and Integrated Systems. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  80. An efficient algorithm for free resources management on the FPGA

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1095-1098 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  81. An efficient and high performance linear recursive variable expansion implementation of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2009, 31st annual international conference of the IEEE engineering in medicine and biology society. s.n. (ed.). Piscataway: IEEE Society, p. 3845-3848 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  82. An efficient realization of forward integer transform in H.264/AVC intra-frame encoder

    Nadeem, M., Wong, S. & Kuzmanov, GK., 2010, 2010 Intl. conf. on embedded computer systems: architectures, modeling and simulation. s.n. (ed.). Piscataway: IEEE Society, p. 71-78 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  83. An efficient software cache for H.264 motion compensation

    Pereira de Azevedo Filho, AP. & Juurlink, B., 2009, 2009 international symposium on system-on-chip proceedings. s.n. (ed.). Piscataway: IEEE Society, p. 147-150 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  84. An empirical comparison of ANSI-C to VHDL compilers: SPARK, ROCCC and DWARV

    Virginia, A., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 388-394 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  85. An energy effective SIMD accelerator for visual pattern matching

    Bira, C., Gugu, L., Hobincu, R., Codreanu, V., Petrica, L. & Cotofana, SD., 2013, 4th International symposium on highly efficient accelerators and reconfigurable technologies. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  86. An energy-aware architectural exploration tool for ARM-based SOCs

    Crisu, D., Cotofana, SD. & Vassiliadis, S., 2001, ProRISC 2001: proceedings. Utrecht: STW Technology Foundation, p. 327-337 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  87. An evaluation of FPGA-based IDS pattern matching techniques

    Sourdis, I., Pnevmatikatos, DN. & Vassiliadis, S., 2005, Proceedings of ProRISC 2005, 16th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: Dutch Technology Foundation, p. 449-453 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  88. An experience with Chalcogenide memristors, and implications on memory and computer applications

    Escudero-López, M., Amat, E., Rubio, A. & Pouyan, P., 2017, 2016 Conference on Design of Circuits and Integrated Systems (DCIS). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  89. An experimental analysis of spot defects in SRAMs: realistic fault models and test

    Hamdioui, S. & van de Goor Ph D, AJ., 2000, Proceedings of the ninth Asian test symposium. DC Young (ed.). Piscataway: IEEE Society, p. 131-138 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  90. An experimental microarchitecture for a superconducting qantum processor

    Fu, X., Rol, M. A., Bultink, C. C., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., DiCarlo, L. & Bertels, K., 14 Oct 2017, MICRO 2017 - 50th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings. IEEE, Vol. Part F131207. p. 813-825 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  91. An implementation of the MPEG-4 ACQ function

    Kuzmanov, G., Vassiliadis, S. & van Eijndhoven, JTJ., 2001, ProRICS 2001: proceedings. Utrecht: STW Technology Foundation, p. 466-469 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  92. An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set

    Gbolagade, KA., Chaves Fernandes, R., Sousa, L. & Cotofana, SD., 2010, IEEE intl. symposium on circuits and systems. Piscataway: IEEE Society, p. 2103-2106 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  93. An improved algorithm for slot selection in the Æthereal Network-on-Chip

    Stefan, RA. & Goossens, KGW., 2011, Proceedings of the Fifth ACM Interconnection Network Architecture, On-Chip Multi-Chip Workshop (INA-OCMC). Flich, J., Bertozzi, D., Skei, T. & Ludovici, D. (eds.). New York, NY, USA: Association for Computing Machinery (ACM), p. 7-10 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  94. An investigation into multicasting

    Manolov, N., Gamil, A. & Wong, JSSM., 2003, Proceedings of ProRISC 2003. s.n. (ed.). Utrecht: STW, p. 523-528 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  95. An o(n) residue number system to mixed radix conversion technique

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 IEEE international symposium on circuits and systems. Piscataway: IEEE Society, p. 521-525 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  96. An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

    Hansson, A. & Goossens, KGW., 2009, 7th IEEE/ACM intl. conf. on hardware/software codesign and system synthesis. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 99-108 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  97. An optimization framework for retargetable compilers

    Panainte, E., Athanasiu, I. & Cotofana, SD., 2001, CSCS-13: proceedings. I Dumitrache & C Buiu (eds.). Bucharest: Editura Politehnica, p. 427-432 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  98. Analog television, WiMAX and DVB-H on the same SoC platform

    Iancu, D., Ye, H., Kotlyar, V., Senthilvelan, M., Glossner, CJ., Nacer, G., Iancu, A. & Takala, J., 2006, 2006 International Symposium on System-on-Chip. s.n. (ed.). Piscataway: IEEE Society, p. 28-31 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  99. Analyses of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, 2008 IEEE International Symposium on Circuits and Systems. s.n. (ed.). s.l., p. 488-491 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  100. Analysis of a reconfigurable network processor

    Kachris, C. & Vassiliadis, S., 2006, Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 192-192

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  101. Analysis of a user-space device-driver for the memcpy hardware

    Campos Soares Borrego, F. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 138-143 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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