1. 2009
  2. Parallel FPGA design of CA CFAR algorithm

    Kyovtorov, VA., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 470-474 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Parallel H.264 decoding on an embedded multicore processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Terechko, A., Hoogerbrugge, J., Alvarez, M. & Ramirez, A., 2009, In : Lecture Notes in Computer Science. 5409, p. 404-418 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Parameter optimization of the adaptive MVDR QR-based beamformer for jamming and multipath suppression in GPS/GLONASS receivers

    Behar, V., Kabakchiev, C., Gaydadjiev, GN., Kuzmanov, GK. & Ganchosov, PN., 2009, 16th Saint Petersburg international conference on integrated navigation systems. s.n. (ed.). s.l.: s.n., p. 325-334 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Performance comparison between linear RVE and linear systolic array implementations of the Smith-Waterman algorithm

    Hasan, L. & Al-Ars, Z., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 451-455 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

    Alvarez, M., Ramirez, A., Valero, M., Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2009, In : Avances en Sistemas e Informatica. 6, 1, p. 219-228 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Performance evaluation of macroblock-level parallelization of H.264 decoding on a cc-NUMA multiprocessor architecture

    Alvarez, M., Ramirez, A., Valero, M., Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2009, Proceedings of the 4th Colombian Computing Conference ( Congreso Colombiano de Computacion). s.n. (ed.). s.l.: s.n., p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. Performance improvement of multimedia kernels by alleviating overhead instructions on SIMD devices

    Shahbahrami, A. & Juurlink, B., 2009, In : Lecture Notes in Computer Science. 5737, p. 389-407 19 p.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Polymorphic architectures - from media processing to supercomputing

    Kuzmanov, GK., 2009, Proceedings of the international conference on computer systems and technologies and workshop for PhD students in computing. Rachev, B. & Smrikarov, A. (eds.). s.l.: s.n., p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Range trees with variable length comparisons

    Sourdis, I., Smet de, R. & Gaydadjiev, GN., 2009, 15th international workshop on high performance switching and routing 2009. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. Range tries for scalable address lookup

    Sourdis, I., Stefanakis, G., Smet de, R. & Gaydadjiev, GN., 2009, ACM/IEEE symposium on architectures for networking and communications systems. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 143-152 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  12. Reconfigurable accelerator for WFS-based 3D-audio

    Theodoropoulos, D., Kuzmanov, GK. & Gaydadjiev, GN., 2009, 23rd IEEE international parallel & distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. Reconfigurable multithreading architectures: a survey

    Zaykov, P., Kuzmanov, GK. & Gaydadjiev, GN., 2009, In : Lecture Notes in Computer Science. 5657, p. 263-274 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Reconfigurable sparse/dense matrix-vector multiplier

    Kuzmanov, GK. & Taouil, M., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 483-488 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  15. Recursive variable expansion for high performance computing

    Nawaz, Z. & Bertels, K., 2009.

    Research output: Contribution to conferencePosterProfessional

  16. Recursive variable expansion for high performance computing

    Nawaz, Z. & Bertels, K., 2009, Advanced computer architecture and compilation for embedded systems. s.n. (ed.). s.l.: HiPEAC, p. 85-88 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. Residue-based code for reliable hybrid memories

    Haron, NZB. & Hamdioui, S., 2009, 2009 IEEE/ACM international symposium on nanoscale architectures. s.n. (ed.). Piscataway: IEEE Society, p. 27-32 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  18. Residue-to-binary converters for the moduli set {2 2n+1, 2 2n, 2n-1}

    Gbolagade, KA., Chaves Fernandes, R., Sousa, L. & Cotofana, SD., 2009, 2nd International Conference on Adaptive Science & Technology. s.n. (ed.). Piscataway: IEEE Society, p. 26-33 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  19. Residue-to-decimal converters for moduli sets with common factors

    Gbolagade, KA. & Cotofana, SD., 2009, 2009 52nd IEEE international midwest symposium on circuits and systems. s.n. (ed.). Piscataway: IEEE Society, p. 624-627 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  20. Resource discovery with dynamic matchmakers in ad hoc grid

    Abdullah, MT., Mhamdi, LL., Pourebrahimi, B. & Bertels, K., 2009, The fourth international conference on systems. Ege, R., Quatttrociocchi, W., Dragomirescu, D. & Dini, O. (eds.). Piscataway: IEEE Society, p. 138-144 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  21. Run-time FPGA testing using hardwired network on chip

    Wahlah, MA. & Goossens, KGW., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 526-529 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  22. Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform

    Sima, VM. & Bertels, K., 2009, 23rd IEEE international parallel & distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  23. Runtime memory allocation in a heterogeneous reconfigurable platform

    Sima, VM. & Bertels, K., 2009, 2009 Intl. conf. on ReConFigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 71-76 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  24. SIMD architectural enhancements to improve the performance of the 2D discrete wavelet transform

    Shahbahrami, A. & Juurlink, B., 2009, 12th Euromicro conference on digital system design architecturs, methods and tools. s.n. (ed.). s.l.: s.n., p. 497-504 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  25. Scalability of macroblock-level parallelism for H.264 decoding

    Alvarez Mesa, M., Ramirez, A., Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B. & Valero, M., 2009, 15th International Conference Parallel and distributed systems (ICPADS 2009). Werner et al., B. (ed.). Piscataway, NJ, USA: IEEE Society, p. 236-243 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  26. Scalar processing overhead on SIMD-only architectures

    Pereira de Azevedo Filho, AP. & Juurlink, B., 2009, 20th IEEE international conference on application-specific systems, architectures and processors. n.s. (ed.). Piscataway: IEEE Society, p. 183-190 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  27. Scan more with memory scan test

    Hamdioui, S. & Al-Ars, Z., 2009, 4th IEEE international conference on design & technology of integrated systems in nanoscale era. s.n. (ed.). Piscataway: IEEE Society, p. 204-209 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  28. Smart Power Management for an Onboard Wireless Sensors and Actuators Network

    Amini, R., Gaydadjiev, GN. & Gill, EKA., 2009, Proceedings AIAA Space 2009 Conference en Exposition. s.n (ed.). Pasadena, California: AIAA, p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  29. Specialization of the cell SPE for media applications

    Meenderinck, CH. & Juurlink, B., 2009, 20th IEEE international conference on application-specific systems, architectures and processors. n.s. (ed.). Piscataway: IEEE Society, p. 46-52 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  30. Suspended gate field effect transistor based power management -a 32- bit adder case study

    Enachescu, M., van Genderen, AJ. & Cotofana, SD., 2009, CAS 2009 proceedings. s.n. (ed.). Piscataway: IEEE Society, p. 561-564 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  31. System level runtime mapping exploration of reconfigurable architectures

    Sigdel, K., Thompson, M., Pimentel, AD., Bertels, K. & Galuzzi, C., 2009, 23rd IEEE international parallel & distributed processing symposium. s.n. (ed.). Piscataway: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  32. Task centric memory management for an on-chip multiprocessor

    Molnos, AM., 2009, Delft. 180 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  33. The Delft reconfigurable VLIW processor

    Wong, S. & Anjam, F., 2009, 17th IEEE International Conference on Advanced Computing and Communications. Balakrishnan, N. (ed.). Piscataway, NJ, USA: IEEE Society, p. 244-251 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  34. The Molen organisation and programming paradigm

    Bertels, K., Beemster, M., Sima, VM., Panainte, E. & Schoorel, M., 2009, Dynamic system reconfiguration in heterogeneous platforms- the Morpheus approach. Voros, N., Rosti, A. & Hubner, M. (eds.). New York: Springer, p. 119-128 270 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientific

  35. The TU Delft sudoku solver on FPGA

    Bok van der, K., Taouil, M., Afratis, P. & Sourdis, I., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 526-529 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  36. Towards a runtime system for reconfigurable computers: a virtualization approach

    Sabeghi, M. & Bertels, K., 2009, Proceedings design, automation and test in Europa. s.n. (ed.). Piscataway: IEEE Society, p. 1576-1579 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  37. Using RRNS codes for cluster faults tolerance in hybrid memories

    Haron, NZB. & Hamdioui, S., 2009, 2009 IEEE international symposium on defect and fault tolerance in VLSI systems. Gizopoulos, D., Tehranipoor, M. & Tragoudas, S. (eds.). Piscataway: IEEE Society, p. 85-93 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  38. Wave field synthesis for 3D audio: architectural prospectives

    Theodoropoulos, D., Ciobanu, CB. & Kuzmanov, GK., 2009, 2009 ACM international conference on computing frontiers & workshops. n.s. (ed.). New York: Association for Computing Machinery (ACM), p. 127-136 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  39. Worst-case bit line coupling backgrounds for open defects in SRAM cells

    Irobi, IS. & Al-Ars, Z., 2009, 20th annual workshop on circuits, systems and signal processing. s.n. (ed.). Utrecht: STW, p. 25-30 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  40. rSesame - a generic system-level runtime simulation framework for reconfigurable architectures

    Sigdel, K., Thompson, M., Galuzzi, C., Pimentel, AD. & Bertels, K., 2009, 2009 intl. conf. on field-programmable technology. Bergmann, N., Diessel, O. & Shannon, L. (eds.). Piscataway: IEEE Society, p. 460-464 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  41. 2008
  42. A cache-based hardware accelerator for memory data movements

    Campos Soares Borrego, F., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  43. A chip multiprocessor accelerator for video decoding

    Meenderinck, CH. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 63-71 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  44. A clustering method for the identification of convex disconnected multiple output instructions

    Galuzzi, C., Theodoropoulos, D. & Bertels, K., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 65-73 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  45. A flexible active-matrix electronic paper with integrated display driver using the u-Czochralski single grain TFT technology

    Chim, WM., Saputra, N., Baiano, A., Long, JR., Ishihara, R. & van Genderen, AJ., 2008, 19th annual workshop on circuits, systems and signal processing. s.n. (ed.). Eindhoven: STW, p. 161-165 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  46. A framework for the automatic generation of instruction-set extensions for reconfigurable architectures

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 280-286 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  47. A hybrid cross layer architecture for wireless protocol stacks

    Chang, Z. & Gaydadjiev, GN., 2008, 2008 international wireless communications and mobile computing conference. s.n. (ed.). Piscataway: IEEE Society, p. 279-285 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  48. A low-cost cache coherence verification method for snooping systems

    Borodin, D. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 219-227 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  49. A memory-optimized bloom filter using an additional hashing function

    Ahmadi, M. & Wong, S., 2008, IEEE GLOBECOM 2008. s.n. (ed.). s.l.: s.n., p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  50. A novel approach for accelerating the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z. & Nawaz, Z., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 40-45 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  51. A partially buffered crossbar packet switching architecture and its scheduling

    Mhamdi, LL., 2008, IEEE Intl. Symposium on Computers and Communications. s.n. (ed.). s.l.: IEEE Society, p. 1-7 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  52. A residue to binary converter for the {2N+2, 2N+1, 2N} moduli set

    Gbolagade, KA. & Cotofana, SD., 2008, Forty-second Asilomar conference on signals, systems, and computers. s.n. (ed.). Piscataway: IEEE Society, p. 1785-1789 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  53. A self-adaptive on-line task placement algorithm for partially reconfigurable systems

    Lu, Y., Thomas, TM., Gaydadjiev, GN., Bertels, K. & Meeuws, RJ., 2008, the 2008 IEEE Intl. Parallel & Distributed Processing Symposium. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  54. A systolic architecture for the Smith-Waterman algorithm with high performance cell design

    Hasan, L., Khawaya, YM. & Bais, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 35-42 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  55. Acceleration of Smith-Waterman using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, KLM., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 915-922 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  56. Accurate profiling and acceleration evaluation of the Smith-Waterman algorithm using the Molen platform

    Hasan, L. & Al-Ars, Z., 2008, IADIS International Conference Applied Computing 2008. Nuno Guimaraes, P. I. (ed.). Portugal: IADIS Press, p. 188-194 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  57. Adaption to dynamic resource availability in ad hoc grids through a learning mechanism

    Pourebrahimi, B. & Bertels, KLM., 2008, 2008 IEEE 11th Intl. Conf. on Computational Science and Engineering. s.n. (ed.). s.l.: s.n., p. 171-178 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  58. Adaptive gaussian mixture for skin color segmentation

    Hassanpour, R., Shahbahrami, A. & Wong, S., 2008, Proceeding of World Academy of Science, Engineering and Technology. s.n. (ed.). s.l.: WASET org., p. 1-6 6 p. (World Academy of Science, Engineering and Technology. Proceedings; vol. 31).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  59. An analysis of internal parameter variations effects on nanoscaled gates

    Martorell, F., Cotofana, SD. & Rubio, A., 2008, In : IEEE Transactions on Nanotechnology. 7, 1, p. 24-33 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  60. An approach for optimal bandwidth allocation in packet processing systems

    Ahmadi, M. & Wong, S., 2008, CNSR 2008 conference. s.n. (ed.). s.l.: s.n., p. 208-214 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  61. An efficient RNS to binary converter using the moduli set {2n+1, 2n, 2n-1}

    Gbolagade, KA. & Cotofana, SD., 2008, Conference on Design of Circuits and Integrated Systems. s.n. (ed.). s.l.: s.n., p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  62. An efficient algorithm for free resources management on the FPGA

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1095-1098 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  63. Analyses of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, 2008 IEEE International Symposium on Circuits and Systems. s.n. (ed.). s.l., p. 488-491 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  64. Analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, 11th Euromicro Conference on Digital System Design, Architectures, Methods and tools. Fanucci, L. (ed.). s.n., p. 189-194 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  65. Applying dataflow analysis to dimension buffers for guaranteed performance in networks on chip

    Hansson, A., Wiggers, M., Moonen, A., Goossens, KGW. & Bekooij, M., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 211-212 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  66. Architecture enhancements for the ADRES coarse-grained reconfigurable array

    Bouwens, F., Berekovic, M., de Sutter, B. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 66-81 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  67. Auction protocols for resource allocations in ad-hoc grids

    Pourebrahimi, B. & Bertels, KLM., 2008, In : Lecture Notes in Computer Science. LNCS5168, p. 520-533 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  68. Automatic instruction-set extensionswith the linear complexity spiral search

    Galuzzi, C., Theodoropoulos, D., Meeuws, RJ. & Bertels, K., 2008, 2008 international conference on reconfigurable computing and FPGAs. s.n. (ed.). Piscataway: IEEE Society, p. 31-36 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  69. Automating defects simulation and fault modeling for SRAMs

    Di Carlo, S., Prinetto, P., Scionti, A. & Al-Ars, Z., 2008, IEEE Intl. High Level Design Validation and Test workshop 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  70. Avoiding conversion and rearrangement overhead in SIMD architectures

    Shahbahrami, A., 2008, 160 p.

    Research output: ThesisDissertation (TU Delft)Scientific

  71. BIST enhancement for detecting bit/byte write enable faults in SOC SCRAMs

    Hamdioui, S., Al-Ars, Z., Jimenez, J. & Calero, J., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-5 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  72. BRAM-LUT tradeoff on a polymorphic DES design

    Chaves Fernandes, R., Donchev, B., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : Lecture Notes in Computer Science. LNCS4917, p. 55-65 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  73. Bandwidth analyses for reusing functional interconnect as test access mechanism

    van den Berg, A., Ren, R., Marinissen, E., Gaydadjiev, GN. & Goossens, KGW., 2008, 13th European test Symposium. s.n. (ed.). Piscataway: IEEE Society, p. 21-26 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  74. Bioinformatics specific cell BE ISA extensions

    Isaza, S. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 52-55 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  75. Bitstream compression techniques for virtex 4 FPGAS

    Stefan, RA. & Cotofana, SD., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 323-328 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  76. Building blocks for fluctuation based calculation in single electron tunneling technology

    Safiruddin, S., Cotofana, SD., Peper, F. & Lee, J., 2008, 2008 eighth IEEE conference on nanotechnology. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  77. CMOS scaling impacts on reliability, what do we understand?

    Seyab, MSK., Haron, NZB. & Hamdioui, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 260-266 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  78. Casta diva-a design for variability platform

    Cotofana, SD. & Meenderinck, CH., 2008, 2008 Intl. Semiconductor Conference. s.n. (ed.). s.l.: IEEE Society, p. 373-376 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  79. Comparison between color and texture features for image retrieval

    Shahbahrami, A., Borodin, D. & Juurlink, B., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 361-371 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  80. Compiler and openMP framework to allow dynamics hardware allocation on reconfigurable platforms

    Sima, VM. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 108-111 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  81. Compositional, dynamic cache management for embedded chip multiprocessors

    Molnos, AM., Cotofana, SD. & Heijligers, MJM., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 991-996 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  82. Cost-efficient SHA hardware accelerators

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 999-1008 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  83. Cross-layer designs architecture for LEO satellite ad hoc network

    Chang, Z. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. 5031, p. 164-176 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  84. Current trends in resource management of recongigurable systems

    Sabeghi, M. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 89-93 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  85. Data locality optimization based on comprehensive knowledge of the cache miss reason: a case study with DWT

    Tao, J. & Shahbahrami, A., 2008, 10th IEEE intl. Conf. on High Performance Computing and Communications. s.n. (ed.). s.l.: IEEE Society, p. 304-311 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  86. Debugging distributed-shared-memory communication at multiple granularities in network on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: EEE, p. 3-12 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  87. Debugging distributed-shared-memory communication at multiple granularities in networks on chip

    Vermeulen, B., Goossens, KGW. & Umrani, S., 2008, Second ACM/IEEE international symposium on networks-on-chip. s.n. (ed.). Piscataway: IEEE Society, p. 3-12 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  88. Defect oriented testing of the strap problem under process variations in DRAMs

    Al-Ars, Z., Hamdioui, S., van de Goor, AJ. & Mueller, G., 2008, Proc. International Test Conference 2008. s.n. (ed.). Washington DC: ITC, p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  89. Design and test of integrated circuits in Nano era: what is next?

    Hamdioui, S., 2008.

    Research output: Contribution to conferenceAbstractScientific

  90. Design trade-offs in customized on-chip crossbar schedulers

    Hur, JY., Wong, S. & Stefanov, TP., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  91. Efficient multicast support in high-speed packet switches

    Mhamdi, LL., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of Networks. 2, 3, p. 28-35 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  92. Efficient tests and DFT for RAM address decoder delay faults

    Hamdioui, S. & Al-Ars, Z., 2008, 3rd International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. 225-230 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  93. Emerging crossbar-based hybrid nanoarchitectures for future computing systems

    Haron, NZB. & Hamdioui, S., 2008, 2nd IEEE Intl. Conf. on Signals, Circuits & Systems. s.n. (ed.). s.l.: IEEE Society, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  94. Evaluation of SRAM faulty behavior under bit line coupling

    Al-Ars, Z. & Hamdioui, S., 2008, 3rd International Design and Test workshop. s.n. (ed.). Piscataway: IEEE Society, p. 231-236 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  95. Exploiting parallelism of deblocking filter of H.264 on DTA architecture

    Giorgi, R., Popovic, Z., Puzovic, N., Pereira de Azevedo Filho, AP. & Juurlink, B., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 55-58 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  96. Extending loop unrolling and shifting for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, Architecture and Compilers Embedded Systems symposium. s.n. (ed.). s.l.: s.n., p. 61-64 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  97. FPGA Implementation of Parallel Histogram Computation

    Shahbahrami, A., Hur, JY., Juurlink, B. & Wong, S., 2008, 2nd HIPEAC workshop on Reconfigurable Computing. s.n. (ed.). HiPEAC, p. 63-72 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  98. FPGA implementation of low-frequency GPR signal algorithm using frequency stepped chirp signals in the time domain.

    Kyovtorov, VA., Kabakchiev, C., Behar, V., Kuzmanov, GK., Garvanov, I. & Doukovska, L., 2008, IEEE Intl. Radar Symposium 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  99. GRAAL: a framework for low-power 3D graphics accelerators

    Juurlink, B., Crisu, D., Antochi, I., Cotofana, SD. & Vassiliadis, S., 2008, In : IEEE Computer Graphics and Applications. 28, 4, p. 63-73 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  100. Generalized matrix method for efficient residue to decimal conversion

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Asia pacific conference on circuits ans systems. s.n. (ed.). Piscataway: IEEE Society, p. 1414-1417 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  101. Generic loop parallelization for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 35-39 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  102. Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z., Nawaz, Z. & Bertels, K., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 135-140 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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