1. 2008
  2. FPGA implementation of low-frequency GPR signal algorithm using frequency stepped chirp signals in the time domain.

    Kyovtorov, VA., Kabakchiev, C., Behar, V., Kuzmanov, GK., Garvanov, I. & Doukovska, L., 2008, IEEE Intl. Radar Symposium 2008. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. GRAAL: a framework for low-power 3D graphics accelerators

    Juurlink, B., Crisu, D., Antochi, I., Cotofana, SD. & Vassiliadis, S., 2008, In : IEEE Computer Graphics and Applications. 28, 4, p. 63-73 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Generalized matrix method for efficient residue to decimal conversion

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Asia pacific conference on circuits ans systems. s.n. (ed.). Piscataway: IEEE Society, p. 1414-1417 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Generic loop parallelization for reconfigurable architectures

    Dragomir, OS. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 35-39 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. Hardware implementation of the Smith-Waterman algorithm using recursive variable expansion

    Hasan, L., Al-Ars, Z., Nawaz, Z. & Bertels, K., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 135-140 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. Hardwired NOC infrastructure with integrated configuration and functional architectures

    Wahlah, MA. & Goossens, KGW., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 122-125 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. Hardwired networks on chip in FPGAs to unify functional and configuration interconnects

    Goossens, KGW., Bennebroek, M., Hur, JY. & Wahlah, MA., 2008, Second ACM/IEEE International Symposium on Networks-on- Chip. s.n. (ed.). Piscataway: IEEE Society, p. 45-54 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. High level quantitative interconnect estimation for early design space exploration

    Meeuws, RJ., Sigdel, K., Yankova, YD. & Bertels, K., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 317-320 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. High quality simulation tool for memory redundancy algorithms

    Yamasaki, K., Hamdioui, S., Al-Ars, Z., van Genderen, AJ. & Gaydadjiev, GN., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 133-138 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. High-bandwidth address generation unit

    Galuzzi, C., Gou, C., Calderon, H., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-12 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  12. ImpBench -a novel benchmark suite for biomedical, microelectronic implants

    Strydis, C., Kachris, C. & Gaydadjiev, GN., 2008, IC - SAMOS 2008. W. Najjar, H. B. (ed.). Piscataway: IEEE Society, p. 82-91 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. Implementing the 2-d wavelet transform on SIMD-enhanced general-purpose processors

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2008, In : IEEE Transactions on Multimedia. 10, 1, p. 43-51 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Instruction-level fault tolerance configurability

    Borodin, D., Juurlink, B., Hamdioui, S. & Vassiliadis, S., 2008, In : Journal of V LSISignal Processing. p. 1-17 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  15. Intelligent merging online task placement algorithm for partially reconfigurable systems

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1346-1351 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  16. Leakage-aware multiprocessor scheduling

    de Langen, PJ. & Juurlink, B., 2008, In : Journal of V LSISignal Processing. p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Loop optimizations for reconfigurable architectures

    Dragomir, OS., Stefanov, TP. & Bertels, KLM., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 215-218 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  18. Loop unrolling and shifting for reconfigurable architectures

    Dragomir, OS., Stefanov, TP. & Bertels, KLM., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 167-171 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  19. Low power microarchitecture with instruction reuse

    Pratas, F., Gaydadjiev, GN., Berekovic, M., Sousa, L. & Kaxiras, S., 2008, Computing Frontiers 2008. s.n. (ed.). s.l.: s.n., p. 149-158 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  20. MRC technique for RNS to decimal conversion using the moduli set{2n+2, 2n+1, 2n}

    Gbolagade, KA. & Cotofana, SD., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 318-321 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  21. Market formulation for resource allocation in an ad-hoc grid

    Pourebrahimi, B., Alima, LO. & Bertels, K., 2008, Second IEEE international conference on self-adaptive and self-organizing systems workshop. s.n. (ed.). Piscataway: IEEE Society, p. 254-259 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  22. Memory copies in multi-level memory systems

    de Langen, PJ. & Juurlink, B., 2008, ASAP 2008 Conference proceedings. s.n. (ed.). IEEE Society, p. 287-292 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  23. Memory organization with multi-pattern parallel accesses

    Vitkovski, A., Kuzmanov, GK. & Gaydadjiev, GN., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1420-1425 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  24. Merged computation for whirlpool hashing

    Chaves Fernandes, R., Kuzmanov, GK., Sousa, L. & Vassiliadis, S., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 272-275 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  25. On incorporating reconfigurable architectures into grid environments using gridsim

    Ahmadi, M. & Wong, S., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 5-10 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  26. On-the-fly attestation of reconfigurable hardware

    Chaves Fernandes, R., Kuzmanov, GK. & Sousa, L., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 71-76 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  27. Online hardware task scheduling and placement algorithm on partially reconfigurable devices

    Thomas, TM., Lu, Y., Bertels, K. & Gaydadjiev, GN., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 306-311 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  28. OpenFPGA corelib core library interoperability effort

    Withlin, M., Poznanovic, D. & Kuzmanov, GK., 2008, In : Parallel Computing. 34, 4-5, p. 231-244 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  29. Optimal unroll factor for reconfigurable architectures

    Dragomir, OS., Panainte, E., Bertels, K. & Wong, S., 2008, In : Lecture Notes in Computer Science. LNCS 4943, p. 4-14 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  30. Optimization of content-based image retrieval functions

    Shahbahrami, A. & Juurlink, B., 2008, Tenth IEEE International Symposium on Multimedia. s.n. (ed.). Piscataway: IEEE Society, p. 607-612 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  31. Parallel Scalability of H.264

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Alvarez, M., Juurlink, B. & Ramirez, A., 2008, First Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG-1). s.n. (ed.). s.l., p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  32. Parallel scalability of video decoders

    Meenderinck, CH., Pereira de Azevedo Filho, AP., Juurlink, B., Alvarez, M. & Ramirez, A., 2008, In : Journal of V LSISignal Processing. p. 1-22 22 p.

    Research output: Contribution to journalArticleScientificpeer-review

  33. Partilially reconfigurable point-to-point FPGA interconnects

    Hur, JY., Wong, S. & Vassiliadis, S., 2008, In : International Journal of Electronics. 95, 7

    Research output: Contribution to journalArticleScientificpeer-review

  34. Performance analyses of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs

    Hur, JY., Goossens, KGW. & Mhamdi, LL., 2008, 16th IFIP/IEEE Intl. Conference on Very Large Scale Integration. s.l. (ed.). s.n., p. 224-232 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  35. Preliminary analyses of the cell BE processor limitations for sequence alignment applications

    Isaza, S., Sanchez, F., Gaydadjiev, GN., Ramirez, A. & Valero, M., 2008, In : Lecture Notes in Computer Science. LNCS5114, p. 53-64 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  36. Profiling of lossless-compression algorithms for a novel biomedical-implant

    Strydis, C. & Gaydadjiev, GN., 2008, ESWEEK 2008 Compilation Proceedings. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 109-114 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  37. Profiling of symmetric -encryption algorithms for a novel biomedical-implant architecture

    Strydis, C., Zhu, D. & Gaydadjiev, GN., 2008, 2008 Computing Frontiers. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 231-240 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  38. Rapid prototyping of the data-driven chip-multiprocessor (D2-CMP) using FPGAs

    Tatas, K., Kyriacou, C., Evripidou, P., Trancoso, P. & Wong, S., 2008, In : Parallel Processing Letters. 18, 2, p. 291-306 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  39. Real-time scheduling using credit-controlled static-priority arbitration

    Akesson, B., Steffens, L., Strooisma, E. & Goossens, KGW., 2008, 14th IEEE intl. Conf. on Embedded and Real-Time Computing Systems and Applications. s.n. (ed.). Piscataway: IEEE Society, p. 3-14 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  40. Reconfigurable architectures in collborative grid computing: an approach

    Wong, S. & Ahmadi, M., 2008, Second Intl. Conf. on Networks for Grid Applicatiojns. s.n. (ed.). s.l.: s.n., p. 1-8 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  41. Regular expression matching in reconfigurable hardware

    Sourdis, I., Vassiliadis, S., Bispo, JCVM. & Cardoso, JMP., 2008, In : Journal of Signal Processing Systems: the journal of DSPtechnologies. 51, 1, p. 99-121 23 p.

    Research output: Contribution to journalArticleScientificpeer-review

  42. Residue number system operands to decimal conversion for 3-moduli sets

    Gbolagade, KA. & Cotofana, SD., 2008, 2008 IEEE Intl. 51st Midwest Symp. on Circuits and Systems. s.n. (ed.). s.l.: IEEE Society, p. 791-794 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  43. Resiurce allocation and openMP extensions for a reconfigurable platform

    Sima, VM., Panainte, E. & Bertels, KLM., 2008, ACACES 2008. s.n. (ed.). s.l.: HiPEAC Network of Excellence, p. 1-3 3 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  44. Resource allocation algorithm and openmp extensions for parallel execution on a heterogeneous reconfigurable platform

    Sima, VM., Panainte, E. & Bertels, KLM., 2008, 2008 Intl. conference on Field Programmable Logic and Applications. Kebschull, U., Platzner, M. & Teich, J. (eds.). Heidelberg: IEEE Society, p. 651-654 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  45. Resource allocation in market-based grids using a history-based pricing mechanism

    Pourebrahimi, B., Ostadzadeh, SA. & Bertels, KLM., 2008, Intl. Joint Conference on Computer, Information, and Systems Sciences, and Engineering. s.n. (ed.). s.l.: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  46. Resource allocation in market-based grids using a history-based pricing mechanism

    Pourebrahimi, B., Ostadzadeh, SA. & Bertels, KLM., 2008, Advances in computer and information sciences and engineering. Sobh, T. (ed.). s.l.: Springer, p. 97-100 590 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  47. Rule-set database inspection: towards knowledge utilization in packet processing

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2008, Proceedings of the third international conference on the latest advances in networks. s.n. (ed.). s.l.: s.n., p. 153-158 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  48. Run-time adaptable architectures for heterogeneous behavior embedded systems

    Schneider Beck, AC., Rutzig, MB., Gaydadjiev, GN. & Carro, L., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 111-124 14 p.

    Research output: Contribution to journalArticleScientificpeer-review

  49. SAMS: Single-affiliation memory-stride parallel memory scheme

    Gou, C., Kuzmanov, GK. & Gaydadjiev, GN., 2008, Computing Frontiers 2008. s.n. (ed.). s.l.: s.n., p. 359-367 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  50. Scalable multigigabit pattern matching for packet inspection

    Sourdis, I., Pnevmatikatos, DN. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 2, p. 156-166 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  51. Self-organizing dynamic ad hoc grids

    Abdullah, MT., Sokolov, S. & Bertels, KLM., 2008, Second IEEE intl. Conf. Self-adaptive and self-organizing systems. s.n. (ed.). s.l.: s.n., p. 10-15 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  52. Single electron tunneling delay insensitive and fluctuation based computation paradigms and circuits

    Safiruddin, S., Cotofana, SD. & Peper, F., 2008, 2008 IEEE/ACM Internl. Symp. on Nanoscale Architectures. s.n. (ed.). Reasearch Publishing Services, p. 69-76 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  53. Suitable cache organizations for a novel biomedical implant processor

    Strydis, C., 2008, International conference on Computer Design. s.n. (ed.). s.l.: IEEE Society, p. 591-598 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  54. System-level design space exploration of dynamic reconfigurable architectures

    Sigdel, K., Thompson, M., Pimentel, A., Stefanov, TP. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS5114, p. 279-288 10 p.

    Research output: Contribution to journalArticleScientificpeer-review

  55. System-level dynamic exploration and mapping for dynamic reconfigurable system

    Sigdel, K., Thompson, M., Pimentel, A., Stefanov, TP. & Bertels, K., 2008, Architecture and Compilers Embedded Systems symposium. s.n. (ed.). s.l.: s.n., p. 49-52 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  56. Test set development for cache memory in modern microprocessors

    Al-Ars, Z., Hamdioui, S., Gaydadjiev, GN. & Vassiliadis, S., 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 6, p. 725-732 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  57. The case for a generic implant processor

    Strydis, C. & Gaydadjiev, GN., 2008, Intl. conference of the IEEE Engineering in Medicine and Biology Society. s.n. (ed.). s.l.: IEEE Society, p. 3186-3191 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  58. The instruction-set extension problem: a survey

    Galuzzi, C. & Bertels, K., 2008, In : Lecture Notes in Computer Science. LNCS4943, p. 209-220 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  59. Towards system level runtime design space exploration of reconfigurable architectures

    Sigdel, K., Thompson, M., Pimentel, A. & Bertels, K., 2008, 19th Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). eindhoven: STW, p. 100-107 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  60. Trade offs in the design of a router with guaranteed and best-effort services for networks on chip

    Rijpkema, E., Goossens, KGW., Radulescu, A. & Dielissen, J., 2008, Design, Automation, and Test in Europe. Lauwereins, R. & Madsen, J. (eds.). Heidelberg: Springer, p. 125-139 515 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  61. Transparent reconfigurable acceleration for heterogeneous embedded applications

    Schneider Beck, AC., Rutzig, MB., Gaydadjiev, GN. & Carro, L., 2008, DATE '08. s.n. (ed.). Kathy Preas. KP publications, p. 1208-1213 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  62. Vectorized AES core for high-throughput secure environments

    Pericas, M., Chaves Fernandes, R., Gaydadjiev, GN., Vassiliadis, S. & Valero, M., 2008, In : Lecture Notes in Computer Science. 5336, p. 83-94 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  63. Versatility of extended subwords and the matrix register file

    Shahbahrami, A., Juurlink, B. & Vassiliadis, S., 2008, In : ACM Transactions on Architecture and Code Optimization. 5, 1, p. 1-29 29 p.

    Research output: Contribution to journalArticleScientificpeer-review

  64. Vision-based hand gesture recognition for human computer interaction: a review

    Hassanpour, R., Wong, S. & Shahbahrami, A., 2008, IADIS Multi Conference on Computer Science and Information Systems. Blashki, K. (ed.). s.l.: IADIS Press, p. 125-132 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  65. Weighted embedded zero tree for scalable video compression

    Choupani, R., Wong, S. & Tolun, MR., 2008, Intl. Conf. on Image Processing, Computer Vission and Pattern Recognition. s.n. (ed.). s.l.: s.n., p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  66. Weighted embedded zero tree for scalable vidoe compression

    Choupani, R., Wong, S. & Tolun, MR., 2008, Proceedings of the 2008 international conference on image processing, computer vision, & pattern recognition. Arabnia, HR. (ed.). USA: CSREA Press, p. 681-684 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  67. Why is CMOS scaling coming to an END?

    Haron, NZB. & Hamdioui, S., 2008, 2008 Third international design and test workshop. Abid, M., Loulou, M., Salem, A., Zorian, Y. & Ivanov, A. (eds.). Piscataway: IEEE Society, p. 98-103 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  68. You can catch more bugs with transaction level honey

    Abramovici, MM., Goossens, KGW., Greenbaum, J., Stollon, N. & Donlin, A., 2008, International Conference on Hardware/Software Codesign and System Synthesis. s.n. (ed.). s.l.: Association for Computing Machinery (ACM), p. 121-124 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  69. pi-VEX: a reconfigurable and extensible softcore VLIW processor

    Wong, S., As van, T. & Brown, G., 2008, 2008 International conference on field-programmable technology. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  70. 2007
  71. (When) will CMPs hit the power wall?

    Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 156-159 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  72. 2007 International conference on field programmable logic and applications

    Bertels, K., Najjar, W., van Genderen, AJ. & Vassiliadis, S., 2007, Piscataway: IEEE Society. 811 p.

    Research output: Book/ReportBookProfessional

  73. A cache architecture for counting bloom filters

    Ahmadi, M. & Wong, S., 2007, 15th International conference on networks. s.n. (ed.). Piscataway: IEEE Society, p. 218-223 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  74. A comparison of two SIMD implementations of the 2D discrete wavelet transform

    Shahbahrami, A. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 169-177 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  75. A dynamic pricing and bidding strategy for autonomous agents in grids

    Pourebrahimi, B., Bertels, K. & Vassiliadis, S., 2007, 6th international joint conference on autonomous agents and multi-agent systems. Joseph S Bergamaschi S, D. Z. (ed.). s.l.: s.l., p. 70-81 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  76. A hardware implementation of the unisim pipeline model

    Stefan, RA. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 259-263 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  77. A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

    Hansson, A., Goossens, KGW. & Radulescu, A., 2007, In : VLSI Design. 2007, art ID 68432, p. 1-16 16 p.

    Research output: Contribution to journalArticleScientificpeer-review

  78. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Reconfigurable Computing: Architectures, Tools and Applications. Koen Bertels Pedro C. Diniz, E. M. & J. M. P. Cardoso (eds.). Heidelberg: Springer, p. 130-141 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  79. A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. LNCS 4419, p. 130-141 12 p.

    Research output: Contribution to journalArticleScientificpeer-review

  80. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, In : Lecture Notes in Computer Science. 4599/2007, p. 283-293 11 p.

    Research output: Contribution to journalArticleScientificpeer-review

  81. A linear complexity algorithm for the generation of multiple input single output instructions of variable size

    Galuzzi, C., Bertels, K. & Vassiliadis, S., 2007, Embedded Computer Systems: Architectures, Modeling, and Simulation. Hämäläinen, Vassiliadis, S., B. M. . (ed.). Heidelberg, Germany: Springer, p. 283-293 11 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  82. A load/store unit for a memcpy hardware accelerator

    Vassiliadis, S., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 537-541 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  83. A memcpy hardware accelarator solution for non cache-line aligned copies

    Campos Soares Borrego, F. & Wong, S., 2007, IEEE18th international conference Application-specific systems, architectures and processors. s.n. (ed.). Piscataway: IEEE Society, p. 397-402 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  84. A monitoring-aware network-on-chip design flow

    Ciordas, C., Hansson, A., Goossens, KGW. & Basten, T., 2007, In : Journal of Systems Architecture.

    Research output: Contribution to journalArticleScientificpeer-review

  85. A new model of placement quality measurement for online task placement

    Lu, Y., Thomas, TM., Gaydadjiev, GN. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). Utrecht: STW, p. 307-310 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  86. A performance model for network processor architectures in packet processing system

    Ahmadi, M. & Wong, S., 2007, 19th IASTED Parallel and distributed computing and systems. Zheng SQ (ed.). Anaheim: ACTA Press, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  87. A profiling framework for design space exploration in heterogeneous systems context

    Sigdel, K., Meeuws, RJ. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 363-368 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  88. A quantative prediction model for hardware/software partitioning

    Meeuws, RJ., Yankova, YD., Bertels, K., Gaydadjiev, GN. & Vassiliadis, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 735-739 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  89. A reconfigurable platform for multi-service edge routers

    Kachris, C. & Vassiliadis, S., 2007, 20th Symposium on integrated circuits and systems design. s.n. (ed.). New York: Association for Computing Machinery (ACM), p. 165-169 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  90. A survey of autonomic computing systems

    Nami, MR. & Bertels, K., 2007, The third international conference on autonomic and autonomous systems. s.n. (ed.). Piscataway: IEEE Society, p. 1-4 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  91. A survey of coarse-grain reconfigurable architectures and CAD tools

    Theodoridis, G., Soudris, D. & Vassiliadis, S., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 89-152 378 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  92. A taxonomy of field-programmable custom computing machines

    Sima, M., Vassiliadis, S. & Cotofana, SD., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 299-378 378 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  93. A two-phase practical parallel algorithm for construction of huffman codes

    Ostadzadeh, SA., Maryam Elahi, B., Tabrizi, ZZ., Amir Moulavi, M. & Bertels, K., 2007, 2007 intl. conf. on Parallel and distributed processing techniques and applicationss. Arabnia HR (ed.). USA: CSREA Press, p. 284-291 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  94. ADRES & DRESC: Architecture and compiler for coarse-grain reconfigurable processors

    Mei, B., Berekovic, M. & Mignolet, J-Y., 2007, Fine- and coarse-grain reconfigurable computing. Vassiliadis, S, S. D. (ed.). Heidelberg: Springer, p. 255-298 378 p.

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  95. Acceleration of biological sequence alignment using recursive variable expansion

    Nawaz, Z., Shabbir, M., Al-Ars, Z. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 233-237 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  96. Agent based local ad hoc grids

    Abdullah, MT. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 284-287 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  97. An OCM based shared memory controller for virtex 4

    Breijer, B., Campos Soares Borrego, F. & Wong, S., 2007, 2007 International conference on field programmable logic and applications. Van Genderen, A Bertels, K., N. W. (ed.). Piscataway: IEEE Society, p. 692-696 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  98. An analysis of basic structures for effective computation in single electron tunneling technology

    Meenderinck, CH. & Cotofana, SD., 2007, In : Romanian Journal of Information Science and Technology. 10, 1, p. 67-83 17 p.

    Research output: Contribution to journalArticleScientificpeer-review

  99. An analysis of rule-set databases in packet classification

    Ahmadi, M., Ostadzadeh, SA. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 110-115 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  100. An empirical comparison of ANSI-C to VHDL compilers: SPARK, ROCCC and DWARV

    Virginia, A., Yankova, YD. & Bertels, K., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 388-394 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  101. Analysis of a user-space device-driver for the memcpy hardware

    Campos Soares Borrego, F. & Wong, S., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 138-143 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  102. Analysis of video filtering on the cell processor

    Pereira de Azevedo Filho, AP., Meenderinck, CH. & Juurlink, B., 2007, Annual Workshop on Circuits, Systems and Signal Processing. s.n. (ed.). utrecht: STW, p. 116-121 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Previous 1...5 6 7 8 9 10 11 12 ...16 Next

ID: 19943