1. 2016
  2. Non-Volatile Look-up Table Based FPGA Implementations

    Xie, L., Du Nguyen, H. A., Taouil, M., Hamdioui, S., Bertels, K. & Alfailakawi, M., 2016, Proceedings : 11th IEEE International Design & Test Symposium. Tourki, R. (ed.). Piscataway, NJ, USA: IEEE, 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  3. Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture

    Haron, A., Yu, J., Nane, R., Taouil, M., Hamdioui, S. & Bertels, K., 2016, 2016 International Conference on High Performance Computing & Simulation (HPCS): 14th Annual Meeting. Piscataway: IEEE, p. 759-766 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  4. Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms

    Houtgast, E., Sima, V., Marchiori, G., Bertels, K. & Al-Ars, Z., 2016, p. 1-1. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  5. Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

    Goossens, S., Chandrasekar, K., Akesson, B. & Goossens, K., 2016, In : IEEE Transactions on Computers. 65, 6, p. 1882-1895 14 p., 7169527.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability

    Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P., Catthoor, F. & Dehaene, W., 2016, Proceedings - IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016). Taskin, B. & Ghosal, P. (eds.). Los Alamitos, CA: IEEE, p. 725-730 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  7. RRAM Variability and its Mitigation Schemes

    Pouyan, P., Amat, E., Hamdioui, S. & Rubio, A., 2016, 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016. Piscataway, NJ: IEEE, p. 141-146 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  8. Read Path Degradation Analysis in SRAM

    Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S., Catthoor, F. & Dehaene, W., 2016, Proceedings - 21st IEEE European Test Symposium, ETS 2016. Danvers, MA: IEEE, p. 1-2 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  9. Run-time Phase Prediction for a Reconfigurable VLIW Processor

    Guo, Q., Sartor, A., Brandon, A., Beck, A. C. S., Zhou, X. & Wong, S., 2016, Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Teich, J. (ed.). Piscataway, NJ: IEEE, p. 1634-1639 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  10. Skeleton-based design and simulation flow for Computation-in-Memory architectures

    Yu, J., Nane, R., Haron, A., Hamdioui, S., Corporaal, H. & Bertels, K., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 165-170 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  11. Synthesizing HDL to Memristor Technology: A Generic Framework

    Du Nguyen, H. A., Xie, L., Taouil, M., Hamdioui, S. & Bertels, K., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 43-48 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  12. TFET NDR Skewed Inverter based Sensing Method

    Gupta, N., Makosiej, A., Vladimirescu, A., Amara, A., Cotofana, S. & Anghel, C., 2016, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Zhao, W. & Moritz, C. A. (eds.). New York: Association for Computing Machinery (ACM), p. 13-14 2 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  13. Testing open defects in memristor-based memories

    Hamdioui, S., Taouil, M. & Haron, NZB., 2016, In : IEEE Transactions on Computers. 64, 1, p. 247-259 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  14. The Fidelity Slider: A User-Defined Method to Trade off Accuracy for Performance in Canny Edge Detector

    Kritchallo, V., Vermij, E., Bertels, K. & Al-Ars, Z., 2016, 11th HiPEAC conference. p. 1-6 6 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

  15. Towards Robust Implementation of Memristor Crossbar Logic Circuits

    Xie, L., 2016, 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). Piscataway., NJ: IEEE, p. 1-4 4 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  16. Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications

    Makosiej, A., Gupta, N., Vakul, N., Vladimirescu, A., Cotofana, S., Mahapatra, S., Amara, A. & Anghel, C., 2016, In : Micro and Nano Letters. 11, 12, p. 828-831 4 p.

    Research output: Contribution to journalArticleScientificpeer-review

  17. Using wavelet transform self-similarity for effective multiple description video coding

    Choupani, R., Wong, S. & Tolun, M., 2016, 10th International Conference on Information, Communications and Signal Processing, ICICS 2015. Piscataway, NJ: IEEE, p. 1-5 5 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  18. 2015
  19. An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm

    Houtgast, E., Sima, VM., Bertels, K. & Al-Ars, Z., 28 Dec 2015, Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XV. Soudris, D. & Carro, L. (eds.). Piscataway, NJ, USA: IEEE Society, p. 221-227 7 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  20. A sparse VLIW instruction encoding scheme compatible with generic binaries

    Brandon, A., Hoozemans, J., Van Straten, J., Lorenzon, A., Sartor, A., Schneider Beck, A. C. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers (IEEE), 7 p. 7393361

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  21. Multiple contexts in a multi-ported VLIW register file implementation

    Hoozemans, J., Johansen, J., Van Straten, J., Brandon, A. & Wong, S., 7 Dec 2015, 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers (IEEE), 6 p. 7393329

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

  22. Memristor Based Computation-in-Memory Architecture for Data-Intensive Applications

    Hamdioui, S., Xie, L., Du Nguyen, H. A., Taouil, M., Bertels, K., Corporaal, H., Jiao, H., Catthoor, F., Wouters, D., Eike, L. & van Lunteren, J., Mar 2015, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition. Nebel, W. (ed.). Piscataway, NJ: IEEE, p. 1718-1725 8 p.

    Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

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