1. 2019
  2. Diminished-1 Fermat Number Transform for Integer Convolutional Neural Networks

    Baozhou, Z., Ahmed, N., Peltenburg, J., Bertels, K. & Al-Ars, Z., 2019, 2019 IEEE 4th International Conference on Big Data Analytics (ICBDA). Guan, S-U., Zhang, K. & Cao, J. (eds.). Piscataway, NJ, USA: IEEE, p. 47-52 6 p. 8713250

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

    Majzoub, S., Saleh, R. A., Ashraf, I., Taouil, M. & Hamdioui, S., 2019, In : IEEE Access. 7, p. 33115-33129 15 p., 8648367.

    Research output: Contribution to journalArticleScientificpeer-review

  4. Enhancing PUF based challenge-response sets by exploiting various background noise configurations

    Martin, H., Peris-Lopez, P., Di Natale, G., Taouil, M. & Hamdioui, S., 2019, In : Electronics (Switzerland). 8, 2, p. 1-14 14 p., 145.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Evaluating POWER Architecture for Distributed Training of Generative Adversarial Networks

    Hesam, A., Vallecorsa, S., Khattak, G. & Carminati, F., 2019, High Performance Computing - ISC High Performance 2019 International Workshops, Revised Selected Papers. Weiland, M., Juckeland, G., Alam, S. & Jagode, H. (eds.). Springer, p. 432-440 9 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 11887 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  6. Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

    Zandrahimi, M., Debaud, P., Castillejo, A. & Al-Ars, Z., 2019, In : Journal of Electronic Testing: Theory and Applications (JETTA). 35, 3, p. 303-315 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Experimental error mitigation via symmetry verification in a variational quantum eigensolver

    Sagastizabal, R., Bonet-Monroig, X., Singh, M., Rol, M. A., Bultink, C. C., Fu, X., Ostroukh, V. P., Muthusubramanian, N., Bruno, A., Beekman, M., Haider, N., O'Brien, T. E. & Dicarlo, L., 2019, In : Physical Review A. 100, 1, 6 p., 010302.

    Research output: Contribution to journalArticleScientificpeer-review

  8. Exploring complex brain-simulation workloads on multi-GPU deployments

    Van Der Vlag, M. A., Smaragdos, G., Al-Ars, Z. & Strydis, C., 2019, In : ACM Transactions on Architecture and Code Optimization. 16, 4, 25 p., 53.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications

    Hoozemans, J., de Jong, R., van der Vlugt, S., Van Straten, J., Elango, U. K. & Al-Ars, Z., 2019, In : Journal of Signal Processing Systems. 91, 1, p. 47-59 13 p.

    Research output: Contribution to journalArticleScientificpeer-review

  10. GPU Accelerated Sequence Alignment with Trace-back for GATK HaplotypeCaller

    Ren, S., Ahmed, N., Bertels, K. & Al-Ars, Z., 2019, In : BMC Genomics. 20, p. 103-116 184.

    Research output: Contribution to journalArticleScientificpeer-review

  11. Graphene Nanoribbon Based Complementary Logic Gates and Circuits

    Jiang, Y., Cucu Laurenciu, N., Wang, H. & Cotofana, S. D., 2019, In : IEEE Transactions on Nanotechnology. 18, p. 287-298 12 p., 8666174.

    Research output: Contribution to journalArticleScientificpeer-review

  12. Hardware-based aging mitigation scheme for memory address decoder

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 2019, 2019 IEEE European Test Symposium (ETS). IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. In-memory database acceleration on FPGAs: a survey

    Fang, J., Mulder, Y. T. B., Hidders, J., Lee, J. & Hofstee, H. P., 2019, In : VLDB Journal.

    Research output: Contribution to journalArticleScientificpeer-review

  14. Increase quantum computing technology readiness level through experimentation in space

    Correale, G., Cerrone, G., Al-Ars, Z. & Bertels, K., 2019. 1 p.

    Research output: Contribution to conferenceAbstractScientific

  15. Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures

    Lao, L., van Wee, B., Ashraf, I., van Someren, J., Khammassi, N., Bertels, K. & Almudever, C. G., 2019, In : Quantum Science and Technology. 4, 1, p. 1-20 20 p., 015005.

    Research output: Contribution to journalArticleScientificpeer-review

  16. Methodology for Application-Dependent Degradation Analysis of Memory Timing

    Kraak, D., Agbo, I., Taouil, M., Hamdioui, S., Weckx, P., Cosemans, S. & Catthoor, F., 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE): Proceedings. IEEE, p. 162-167 6 p. 8715143

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. Multi-target Regression Approach for Predictive Maintenance in Oil Refineries using Deep Learning

    Helmiriawan, H. & Al-Ars, Z., 2019, In : International Journal of Neural Networks and Advanced Applications. 6, p. 18-24 7 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Non-Equilibrium Green Function-based Verilog-A Graphene Nanoribbon Model

    Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO). Quinn, A., Li, G., Li, W. & Mathewson, A. (eds.). Piscataway, NJ, USA: IEEE, p. 1-4 4 p. 8626396

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  19. On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

    Jiang, Y., Laurenciu, N. C. & Cotofana, S. D., 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 5, p. 1948-1959 12 p., 8574057.

    Research output: Contribution to journalArticleScientificpeer-review

  20. Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing

    Wu, L., Rao, S., Cardoso Medeiros, G., Taouil, M., Marinissen, E. J., Yasin, F., Couet, S., Hamdioui, S. & Kar, G. S., 2019, 2019 IEEE European Test Symposium (ETS): Proceedings. Danvers: IEEE, p. 1-6 6 p. 8791518

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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