1. 2017
  2. An experimental microarchitecture for a superconducting qantum processor

    Fu, X., Rol, M. A., Bultink, C. C., Van Someren, J., Khammassi, N., Ashraf, I., Vermeulen, R. F. L., De Sterke, J. C., Vlothuizen, W. J., Schouten, R. N., García Almudever, C., DiCarlo, L. & Bertels, K., 14 Oct 2017, MICRO 2017 - 50th Annual IEEE/ACM International Symposium on Microarchitecture Proceedings. IEEE, Vol. Part F131207. p. 813-825 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Using a Polymorphic VLIW Processor to Improve Schedulability and Performance for Mixed-criticality Systems

    Hoozemans, J., van Straten, J. & Wong, S., Aug 2017, 2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). Danvers: IEEE, p. 1-9 9 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. Restless Tuneup of High-Fidelity Qubit Gates

    Rol, M. A., Bultink, C. C., O'Brien, T. E., De Jong, S. R., Theis, L. S., Fu, X., Luthi, F., Vermeulen, R. F. L., De Sterke, J. C., Bruno, A., Deurloo, D., Schouten, R. N., Wilhelm, F. K. & Dicarlo, L., 24 Apr 2017, In : Physical Review Applied. 7, 4, 041001.

    Research output: Contribution to journalArticleScientificpeer-review

  5. Improved Dynamic Cache Sharing for Communicating Threads on a Runtime-Adaptable Processor

    Hoozemans, J., Lorenzon, A., Schneider Beck, A. C. & Wong, S., Jan 2017, p. 1-9. 9 p.

    Research output: Contribution to conferenceAbstractScientific

  6. A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons

    Yu, J., Hogervorst, T. & Nane, R., 2017, GLSVLSI '17 Proceedings of the on Great Lakes Symposium on VLSI 2017 . New York: Association for Computing Machinery (ACM), p. 71-76 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. An experience with Chalcogenide memristors, and implications on memory and computer applications

    Escudero-López, M., Amat, E., Rubio, A. & Pouyan, P., 2017, 2016 Conference on Design of Circuits and Integrated Systems (DCIS). Piscataway, NJ: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations

    Smaragdos, G., Chatzikonstantis, G., Kukreja, R., Sidiropoulos, H., Rodopoulos, D., Sourdis, I., Al-Ars, Z., Kachris, C., Soudris, D., De Zeeuw, C. I. & Strydis, C., 2017, In : Journal of Neural Engineering. 14, 6, p. 1-15 15 p., 066008.

    Research output: Contribution to journalArticleScientificpeer-review

  9. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Patent No. US 9,824,753, Priority date 21 Oct 2015

    Research output: PatentOther research output

  10. Computing device for "big data" applications using memristors

    Hamdioui, S., Taouil, M. & Bertels, K., 2017, IPC No. G11C, Priority date 21 Oct 2015, Priority No. US 2017/0117041

    Research output: PatentOther research output

  11. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

    Sartor, A. L., Lorenzon, A. F., Carro, L., Kastensmidt, F., Wong, S. & Beck, A. C. S., 2017, In : ACM Journal on Emerging Technologies in Computing Systems. 13, 2, p. 13:1-13:21 21 p.

    Research output: Contribution to journalSpecial issueScientificpeer-review

  12. Exploring ILP and TLP on a Polymorphic VLIW Processor

    Brandon, A., Hoozemans, J., van Straten, J. & Wong, S., 2017, Architecture of Computing Systems - ARCS 2017: 30th International Conference Proceedings. Knoop, J., Karl, W., Schulz, M., Inoue, K. & Pionteck, T. (eds.). Cham: Springer, p. 177-189 13 p. (Lecture Notes in Computer Science ; vol. 10172).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  13. Fast and accurate workload-level neural network based IC energy consumption estimation

    Cucu Laurenciu, N. & Cotofana, S., 2017, SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design. IEEE, p. 1-4 4 p. 7981598

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  14. GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization

    Ren, S., Bertels, K. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 497-502 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  15. Haar-based interconnect coding for energy effective medium/long range data transport

    Cucu Laurenciu, N. & Cotofana, S., 2017, Proceedings - 30th IEEE International System on Chip Conference, SOCC 2017. Alioto, M., Li, H., Becker, J., Schlichtmann, U. & Sridhar, R. (eds.). Piscataway, NJ: IEEE, p. 375-380 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  16. High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL

    Houtgast, E., Sima, V. & Al-Ars, Z., 2017, 2017 IEEE 17th International Conference on BioInformatics and BioEngineering (BIBE). Piscataway: IEEE, p. 492-496 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  17. Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

    Kraak, D., Taouil, M., Agbo, I., Hamdioui, S., Weckx, P., Catthoor, F. & Cosemans, S., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 12, p. 3464-3472 9 p.

    Research output: Contribution to journalArticleScientificpeer-review

  18. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

    Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Kükner, H., Weckx, P., Raghavan, P. & Catthoor, F., 2017, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1444-1454 11 p., 7819518.

    Research output: Contribution to journalArticleScientificpeer-review

  19. Interconnect Networks for Resistive Computing Architectures

    Du Nguyen, H. A., Xie, L., Yu, J., Taouil, M. & Hamdioui, S., 2017, 2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS). Danvers: IEEE, p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  20. LDPC-Based Adaptive Multi-Error Correction for 3D Memories

    Lefter, M., Voicu, G., Marconi, T., Savin, V. & Cotofana, S., 2017, 2017 IEEE International Conference on Computer Design (ICCD). IEEE, Vol. Piscataway. p. 265-268 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  21. Low cost multi-error correction for 3D polyhedral memories

    Lefter, M., Marconi, T., Voicu, G. & Cotofana, S., 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures. IEEE, p. 13-18 6 p. 8053722

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Previous 1...3 4 5 6 7 8 9 10 ...79 Next

ID: 19943